SerDes Relocation in Semiconductor Memory Interface Area
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing production costs and chip size due to the surface area occupied by the SerDes device in the peripheral area, which hinders miniaturization and cost efficiency.
Innovation Solution
The SerDes device is relocated from the data path logic area to the interface area, specifically placed in surplus areas within the interface area, allowing for a reduction in the surface area of the peripheral region and utilizing this space to minimize the overall size and production costs of the semiconductor memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SerDes device is placed in the peripheral area (data path logic area), then the device can perform data transmission functions, but the chip size increases due to the surface area occupied in the peripheral region
Solution Approach 1:
The SerDes device is extracted from the peripheral area (data path logic area) and relocated to the interface area. This separation removes the data transmission function from the peripheral region, thereby reducing the surface area occupied in the peripheral area and minimizing overall chip size while maintaining the SerDes functionality in the interface area.
Solution Approach 2:
The layout is reorganized by changing the spatial dimension of component placement. Instead of placing the SerDes device in the peripheral area surrounding the memory cell array, it is positioned in the interface area at the boundary of the chip, utilizing previously underutilized space and optimizing the spatial distribution of functional blocks.
2Reliability
If the SerDes device occupies surface area in the peripheral area, then data transmission can be performed, but production cost increases due to larger chip area
Solution Approach 1:
The SerDes device is extracted from the peripheral area and relocated to the interface area. This reduces the total chip area required, which directly lowers production costs associated with larger semiconductor substrates, while the data transmission function remains intact in the interface region.
Solution Approach 2:
The spatial parameter (location) of the SerDes device is changed from the peripheral area to the interface area. This parameter change optimizes the area utilization and reduces the overall chip footprint, leading to cost-effective manufacturing while preserving functional performance.
3Area of stationary object
If the peripheral area is minimized by relocating SerDes to the interface area, then chip size is reduced, but the interface area must accommodate additional functionality
Solution Approach 1:
The interface area is designed to serve multiple functions: it accommodates the SerDes device for data transmission, provides I/O pad connections, and handles signal routing. By making the interface area multi-functional, the design consolidates several functions into one region, reducing the need for separate dedicated spaces and thereby minimizing the peripheral area.
Solution Approach 2:
The SerDes device is merged with the interface area structure, combining data transmission functionality with the existing I/O interface infrastructure. This consolidation eliminates the need for separate peripheral space for the SerDes device, reducing overall chip area while integrating multiple functions efficiently in the interface region.
Data Source
AI summary
A semiconductor memory device may include a memory cell array area, a peripheral area, and an interface area. The memory cell array area may include at least one memory plane. The peripheral area may be formed adjacent to one side of the memory cell array area. The interface area may be formed adjacent to one side of the peripheral area and include a plurality of data input/output pads. The peripheral area may include a data path logic area formed between the memory cell array area and the interface area. The interface area may include at least one SerDes (serializer/deserializer) area configured to transmit, to the memory cell array area, data inputted through the data input/output pads, or output, through the data input/output pads, data received from the memory cell array.