SerDes Routing for Digital Beam Forming Antenna Arrays

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional array antennas face challenges with data latency and memory usage due to the size of the array and the complexity of data synchronization in microwave and millimeter wave applications, particularly in large array antennas with hundreds or thousands of antenna elements.

Innovation Solution

The implementation of a connection network of Serializer/Deserializer (SerDes) links between Digital Beam Forming (DBF) devices on a panel, which includes various routing configurations and failure recovery mechanisms, such as re-routing, to optimize data latency and memory usage, and the arrangement of antenna elements on a triangular lattice to reduce the number of elements required, thereby simplifying the array antenna architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional array antenna architecture is used with hundreds or thousands of antenna elements, then coverage and signal quality are improved, but data latency and memory usage increase significantly

Engineering Contradiction:
Improvesignal qualityVSAvoiddata latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the large array antenna into multiple sub-arrays or groups, each processed by separate DBF devices. This segmentation allows parallel processing of data from different antenna groups, reducing the overall data latency while maintaining the coverage benefits of a large array configuration

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical processing architecture that adds a new dimension to data flow management. By organizing DBF devices in multiple stages or layers with optimized interconnect routing, the system reduces memory access latency and data traversal time without compromising signal quality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If conventional array antenna architecture is used with hundreds or thousands of antenna elements, then coverage and signal quality are improved, but memory usage increases significantly

Engineering Contradiction:
Improvesignal qualityVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the antenna array into multiple sub-arrays, each handled by dedicated DBF devices with local memory. This distribution of memory requirements across multiple devices reduces the memory burden on any single device and allows for more efficient memory management throughout the system

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a hierarchical memory architecture that adds spatial and temporal dimensions to memory organization. By structuring memory access patterns across multiple DBF devices and processing stages, the system reduces peak memory usage and improves memory efficiency while maintaining signal quality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If antenna elements are arranged in conventional configurations, then coverage is achieved, but grating lobes are generated and complexity increases

Engineering Contradiction:
Improvecoverage areaVSAvoidarray architecture complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent employs asymmetric or non-uniform spacing arrangements of antenna elements within sub-arrays, which helps suppress grating lobe formation while maintaining broad coverage. This asymmetric configuration reduces the regularity that causes grating lobes in conventional uniform arrays, thereby simplifying the overall system requirements

Inventive Principle:
Principle #4Asymmetry

4Area of stationary object

If antenna elements are arranged in conventional configurations, then coverage is achieved, but grating lobes are generated and power consumption increases

Engineering Contradiction:
Improvecoverage areaVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSUse of energy by stationary object

Solution Approach 1:

The asymmetric element spacing configuration suppresses grating lobes, which reduces the need for high-power transmission to overcome interference patterns. This results in lower overall power consumption while maintaining the required coverage area

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS11424796B1Panel Serializer/Deserializer (SerDes) routing
Publication Date: 2022.08.23 AMAZON TECH INC
  • US11424796B1 patent drawing
  • US11424796B1 patent drawing
  • US11424796B1 patent drawing

AI summary

Technologies directed to Serializer/Deserializer (SerDes) connections and SerDes routing between digital beam forming (DBF) devices of a panel with an array of antenna elements, such as on satellite User Link panels, are described. A first DBF device is coupled to a first modem over a first SerDes link and coupled to RFFE circuitry. A second DBF device is coupled to the first DBF device over a second SerDes link. Each of the DBF devices is coupled to multiple antenna elements. The DBF devices route data between the modem and the other DBF devices, such as in a chain of DBF devices.