SERDES Sampler Circuit with Integrated Feedback Equalization
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Solution Overview
Problem
Communication systems face challenges in efficiently receiving high-bandwidth and high-data-transition-rate signals due to inter-symbol interference (ISI) and signal distortion caused by low-pass channels, which existing serializer/deserializer (SERDES) technologies struggle to address effectively.
Innovation Solution
The proposed solution involves a receiving circuit with a sampler circuit and a decision feedback equalization (DFE) circuit that forms a feedback loop to reduce ISI, using a current-mode sense amplifier topology and a feedback equalization circuit with differential pairs of transistors to adjust the signal based on previous digital outputs, maintaining zero static power consumption and minimizing common-mode noise impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a feedback equalization circuit is added to reduce ISI, then signal reception performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the feedback equalization circuit with the sampler circuit by coupling the feedback equalization circuit to the intermediate node of the sampler circuit. This integration allows the feedback equalization function to be implemented within the existing sampling structure, reducing overall device complexity while maintaining signal reception performance improvement through ISI reduction.
Solution Approach 2:
The patent implements a feedback equalization circuit that uses previous digital outputs to generate feedback signals that adjust the sampling process. This feedback mechanism reduces inter-symbol interference by compensating for channel effects, thereby improving signal reception performance without requiring a completely separate equalization system.
2Use of energy by moving object
If a current-mode sense amplifier topology is used, then static power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces the traditional voltage-mode sense amplifier with a current-mode sense amplifier topology. This substitution uses current signals instead of voltage signals for the sampling process, which inherently reduces static power consumption. The current-mode operation allows for lower power dissipation while maintaining the necessary signal detection accuracy through current-based comparison mechanisms.
Data Source
AI summary
Aspects of the disclosure provide an apparatus that includes interface circuitry with a serializer/deserializer (SERDES) circuit. The interface circuitry includes a receiving circuit that receives a signal that carries a sequence of digital values. The receiving circuit includes sampler circuit and a feedback equalization circuit. The sampler circuit includes an amplifying portion and a latch portion coupled at an intermediate node. The amplifying portion varies, with an amplifying gain, an intermediate signal at the intermediate node in response to an input signal to the sampler circuit, and the latch portion generates a digital output based on the intermediate signal at the intermediate node. The feedback equalization circuit is coupled to the intermediate node to vary the intermediate signal at the intermediate node based on a previous digital output from the latch portion of the sampler circuit.