SerDes Clock Recovery Sampling Scope for SBR Reconstruction
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Solution Overview
Problem
Existing solutions for characterizing and debugging communication channels in high-speed, high-bandwidth systems are complex, power-intensive, and area-consuming, making it difficult to reconstruct continuous time Single Bit Response (SBR) for accurate channel analysis.
Innovation Solution
A modified clock recovery loop in a DSP for SerDes interfaces is configured to operate in a sampling scope mode, allowing for fractional lock and oversampling, enabling the reconstruction of high-resolution continuous time SBR without significant hardware additions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing solutions for characterizing communication channels are used, then channel analysis can be performed, but the system complexity, power consumption, and area consumption increase significantly
Solution Approach 1:
The clock recovery loop is designed to perform multiple functions: normal clock recovery operation and sampling scope mode for SBR measurement. By reconfiguring the existing loop to operate in different modes, the patent eliminates the need for separate dedicated measurement hardware, thereby reducing device complexity while maintaining measurement precision
Solution Approach 2:
The system uses its own internal clock recovery loop to perform SBR measurements without requiring external specialized equipment. The clock recovery loop serves itself by being reconfigured into sampling scope mode, utilizing existing resources (ADC, DLL, feedback path) to achieve channel characterization independently
2Measurement precision
If existing solutions for characterizing communication channels are used, then channel analysis can be performed, but power consumption increases significantly
Solution Approach 1:
The clock recovery loop is designed to perform multiple functions: normal clock recovery operation and sampling scope mode for SBR measurement. By reconfiguring the existing loop to operate in different modes, the patent eliminates the need for separate dedicated measurement hardware, thereby reducing device complexity while maintaining measurement precision
Solution Approach 2:
The system uses its own internal clock recovery loop to perform SBR measurements without requiring external specialized equipment. The clock recovery loop serves itself by being reconfigured into sampling scope mode, utilizing existing resources (ADC, DLL, feedback path) to achieve channel characterization independently
3Measurement precision
If existing solutions for characterizing communication channels are used, then channel analysis can be performed, but the hardware area consumption increases significantly
Solution Approach 1:
The clock recovery loop is designed to perform multiple functions: normal clock recovery operation and sampling scope mode for SBR measurement. By reconfiguring the existing loop to operate in different modes, the patent eliminates the need for separate dedicated measurement hardware, thereby reducing device complexity while maintaining measurement precision
Solution Approach 2:
The system uses its own internal clock recovery loop to perform SBR measurements without requiring external specialized equipment. The clock recovery loop serves itself by being reconfigured into sampling scope mode, utilizing existing resources (ADC, DLL, feedback path) to achieve channel characterization independently
4Measurement precision
If the clock recovery loop operates in sampling scope mode with fractional lock, then continuous time SBR can be reconstructed with high resolution, but the operating conditions become more complex
Solution Approach 1:
The clock recovery loop is designed to dynamically switch between normal operation mode and sampling scope mode. The ability to reconfigure the loop's operation mode allows it to adapt to different measurement requirements, achieving high-resolution SBR reconstruction when needed while maintaining simple operation during normal data transmission
Solution Approach 2:
The sampling scope mode utilizes periodic sampling at fractional multiples of the baud rate to reconstruct continuous time SBR. By employing periodic action with specific sampling timing, the system achieves high measurement precision without requiring continuous complex operations
Data Source
AI summary
A clock recovery loop in a digital signal processor for a serializer-deserializer data interface can be modified to achieve fractional lock and operate in a sampling scope mode. The clock recovery loop can control a phase locked loop to produce a clock signal that is at a rational fraction of a baud rate. The clock signal can be used by time-interleaved analog-to-digital converters to achieve oversampling of a periodic signal received over a receive channel. The samples can be used to reconstruct a continuous time signal bit response to characterize or debug the receive channel.