SerDes Transmitter Self-Test Using M/N PLL Sampling
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Solution Overview
Problem
Current methods for testing digital communication transmitter circuits require a full receiver, which is not feasible for die-to-die communication before the transmitter and receiver are coupled, leading to inefficiencies in testing and potential missed data paths.
Innovation Solution
Implementing a phase-lock loop (PLL) with an M/N phase-lock loop to generate an asynchronous sample clock signal, allowing the transmitter to test itself by sampling and error-checking a predetermined data pattern without a receiver, enabling at-speed testing and reducing power/area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full receiver is used to test the transmitter, then data transmission accuracy can be verified, but power consumption and area requirements increase significantly
Solution Approach 1:
The patent extracts only the essential testing functionality from a full receiver by implementing a simplified loop-back mechanism that routes transmitted data back to the transmitter input. This allows verification of data transmission accuracy without requiring complete receiver functionality, thereby reducing power consumption while maintaining measurement precision.
Solution Approach 2:
The transmitter is designed to perform both its primary function of data transmission and its secondary function of self-testing using the same hardware components. By routing the transmitted data back through the physical interface and using the transmitter's own reception capability for self-verification, the system achieves multi-functionality without additional power-hungry receiver components.
2Measurement precision
If a full receiver is used to test the transmitter, then all data paths can be covered, but the device area increases
Solution Approach 1:
The patent extracts only the essential testing functionality from a full receiver by implementing a simplified loop-back mechanism that routes transmitted data back to the transmitter input. This allows verification of data transmission accuracy without requiring complete receiver functionality, thereby reducing power consumption while maintaining measurement precision.
Solution Approach 2:
The transmitter is designed to perform both its primary function of data transmission and its secondary function of self-testing using the same hardware components. By routing the transmitted data back through the physical interface and using the transmitter's own reception capability for self-verification, the system achieves multi-functionality without additional power-hungry receiver components.
3Productivity
If testing is performed before transmitter and receiver are coupled, then testing efficiency improves, but the test setup becomes more complex
Solution Approach 1:
The patent merges the testing functionality with the transmitter's existing hardware by implementing a loop-back mechanism that uses the same physical interface and internal components. This eliminates the need for separate test equipment and complex external test setups, allowing efficient pre-coupling testing while maintaining simple system architecture.
Solution Approach 2:
The transmitter performs self-testing by routing its own transmitted data back to its input and comparing it with the expected data pattern. This self-service capability eliminates the need for external test equipment and complex test setups, thereby improving testing efficiency while reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective self-testing of transmitters without a receiver, ensuring data transmission accuracy and covering all data paths, while reducing power and area usage by eliminating the need for a loop-back receiver.
Implementation Method 1
an M/N phase-lock loop to generate an asynchronous sample clock signal
Implementation Method 2
The M/N PLL divides the reference clock signal by N and multiplies by M to generate the sample clock signal
Data Source
AI summary
Various embodiments provide for testing a transmitter using a phase-lock loop, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer using a sample clock signal generated by an M/N phase-lock loop (PLL); and using a pattern checker to error check the sampled data to determine whether the data transmission test passes.