SERDES Receiver Clock Skew Calibration Using Test Delays

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Solution Overview

Problem

Existing data communication systems, particularly SERDES receivers, are inadequate in handling high-data communication applications due to skew errors caused by poor alignment between edge samples and data samples, leading to inefficiencies and high power consumption.

Innovation Solution

A mechanism is introduced to determine an adjustment delay by sampling edge and data samples at different test delays at a calibration frequency distinct from the sampling frequency, selecting the test delay with the least average position as the adjustment delay to minimize skew errors, which is then used as a parameter for sampling at the sampling frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional SERDES receivers are used, then basic data communication is supported, but skew errors occur due to poor alignment between edge samples and data samples

Engineering Contradiction:
Improveskew error reductionVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing delay calibration before actual data sampling. The system pre-determines optimal delay values for the edge sampler and data sampler by evaluating multiple candidate delays and selecting those that minimize skew errors. This preliminary calibration ensures proper alignment is established before high-speed data communication begins, preventing skew errors rather than correcting them during operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs parameter changes by systematically varying the delay parameters of the edge sampler and data sampler across multiple candidate values during calibration. The system changes these delay parameters to evaluate different alignment scenarios, measures the resulting skew errors, and selects the parameter combination that optimizes alignment precision and minimizes skew errors for reliable communication.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If larger devices are used to drive clocks for better alignment, then skew error correction improves, but power consumption increases

Engineering Contradiction:
Improveskew error correctionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent uses parameter changes to optimize delay alignment by adjusting timing parameters through digital control rather than increasing physical clock driver strength. The system evaluates multiple delay parameter combinations and selects optimal values that achieve skew error correction without requiring additional power-hungry hardware components.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces mechanical/physical clock driving approaches with digital parameter adjustment mechanisms. Instead of using larger physical devices to drive clocks for better alignment, the system substitutes digital delay calibration that adjusts timing parameters software-controlled, significantly reducing power consumption while achieving the same skew error correction effect.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If delay calibration is performed at sampling frequency, then alignment is optimized, but calibration time and complexity increase

Engineering Contradiction:
Improvealignment precisionVSAvoidcalibration time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by performing delay calibration at a reduced frequency rather than full sampling frequency. The system conducts the complete delay calibration process at a lower frequency where timing measurements are easier to capture and process, then applies the calibrated delay parameters to the full-speed sampling operation. This approach achieves the necessary alignment precision while significantly reducing calibration time and complexity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9461814B1High-speed clock skew correction for serdes receivers
Publication Date: 2016.10.04 MARVELL ASIA PTE LTD
  • US9461814B1 patent drawing
  • US9461814B1 patent drawing
  • US9461814B1 patent drawing

AI summary

The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.