SerDes Driver Slice Resistance Calibration for PVT Matching
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Solution Overview
Problem
High-speed SerDes designs face challenges in maintaining consistent performance across process, voltage, and temperature (PVT) corners due to varying unit slice resistance, leading to resistance-matching resolution loss and increased output capacitance, which affects bandwidth and power consumption.
Innovation Solution
An analog technique is employed to maintain a fixed number of active driver slices, using parallel driver slices with signal generator circuits and bias circuits to calibrate the output resistance of each slice to a desired value, ensuring consistent performance across PVT corners and minimizing resolution loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital calibration loop is used to determine the number of slices, then the output resistance can be adjusted to match transmission line impedance, but the output capacitance increases due to using a large number of slices to accommodate PVT corner variations
Solution Approach 1:
The patent changes the control parameter from discrete slice selection to continuous resistance adjustment. By using an analog calibration loop that continuously adjusts the resistance of each slice rather than selecting discrete numbers of slices, the system achieves accurate impedance matching without increasing the number of active slices, thereby reducing output capacitance while maintaining reliability across PVT corners
Solution Approach 2:
The patent implements a dynamic analog calibration loop that continuously adjusts slice resistances in real-time based on feedback, rather than using a static digital selection of slice counts. This dynamic adjustment allows the system to maintain optimal impedance matching across varying PVT conditions without requiring a fixed large number of slices, thus reducing output capacitance while preserving matching accuracy
2Reliability
If the number of slices is increased to cover PVT corner variations, then the output resistance matching is improved, but the gate capacitance seen by pre-driver signals increases
Solution Approach 1:
The patent transforms the approach from changing the quantity of slices to changing the resistance parameter of each slice. By using an analog calibration loop that adjusts the resistance value of each slice continuously, the system achieves comprehensive PVT corner coverage with a fixed, smaller number of slices, thereby reducing the total gate capacitance loaded on pre-driver signals while maintaining reliability
3Adaptability or versatility
If a digital calibration loop is used to calibrate resistance, then the slice number can vary over PVT corners, but resistance-matching resolution loss occurs due to inability to exactly divide slices into required ratios
Solution Approach 1:
The patent replaces the mechanical/discrete slice selection mechanism with an analog resistance adjustment mechanism. Instead of selecting discrete numbers of slices (mechanical approach), the system uses continuous analog resistance control via calibration loops, enabling precise resistance matching without the quantization errors inherent in digital slice selection, thus eliminating resolution loss while maintaining PVT adaptability
Solution Approach 2:
The patent changes from discrete parameter selection (slice count) to continuous parameter adjustment (resistance value). The analog calibration loop continuously adjusts the resistance parameter of each slice, providing fine-grained control that eliminates the quantization steps inherent in digital slice selection, thereby achieving high-precision resistance matching while adapting to PVT variations
4Reliability
If more slices are used to ensure impedance matching across all PVT corners, then the matching coverage is improved, but the power consumption increases due to pre-driver signals being sent to more slices
Solution Approach 1:
The patent changes the approach from increasing the number of active slices to adjusting the resistance parameter of each slice. By using an analog calibration loop that optimizes resistance values, the system achieves comprehensive PVT corner coverage with a fixed, smaller number of slices, thereby reducing pre-driver power consumption while maintaining matching coverage through parameter optimization rather than quantity increase
Data Source
AI summary
A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.