SERDES Slip Circuit for Glitch-Free Serial Data Alignment
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Solution Overview
Problem
In multi-SERDES channel systems, synchronizing data across different sets of parallel data streams is complex and challenging due to the complexity of circuitry required for synchronization in the parallel domain, making it desirable to perform synchronization in the serial domain before conversion.
Innovation Solution
The implementation of a SERDES system with a slip circuit that uses delay control signals to align incoming serial data streams by delaying them by one bit in the serial domain, utilizing a phase detector, slip circuit, and deserializer to produce synchronized parallel data streams, avoiding glitches through a 3-to-1 mux configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data synchronization is performed on parallel data streams, then data alignment across multiple SERDES channels is achieved, but circuit complexity increases significantly
Solution Approach 1:
The patent applies preliminary action by performing data synchronization in the serial domain before the serial-to-parallel conversion. The slip circuit adjusts timing of serial data streams using delay control signals generated by the PCS, ensuring synchronization is established beforehand, thus avoiding the need for complex parallel domain synchronization circuitry.
Solution Approach 2:
The patent uses the PCS (Physical Coding Sublayer) as an intermediary to generate delay control signals that regulate the timing of serial data streams. This intermediary component coordinates timing adjustments across multiple SERDES channels, enabling synchronization without direct complex interconnection between parallel data stream processors.
2Manufacturing precision
If timing adjustment is performed in parallel domain, then data alignment is achieved, but the risk of glitches and timing errors increases
Solution Approach 1:
The system performs timing adjustment in the serial domain before conversion to parallel domain. The slip circuit modifies serial data stream timing using control signals from the PCS, ensuring precise alignment is established beforehand, which prevents timing errors and glitches that would occur with post-conversion adjustment.
Solution Approach 2:
The patent replaces complex mechanical-like parallel domain timing adjustment mechanisms with a simpler serial domain control approach. Instead of physically adjusting parallel data stream timing through complex circuitry, the system uses digital delay control signals in the serial domain to achieve the same timing alignment effect more reliably.
3Reliability
If multiple SERDES channels are synchronized in parallel domain, then data coherence is achieved, but the number of required circuit components increases
Solution Approach 1:
The patent merges the synchronization function into the serial domain processing stage. The PCS generates centralized delay control signals that coordinate multiple SERDES channels before they convert to parallel streams. This consolidation reduces the need for separate synchronization circuitry in each parallel channel, thereby reducing total component count while maintaining data coherence.
Solution Approach 2:
The PCS serves multiple functions: it encodes/decodes data and simultaneously generates delay control signals for timing synchronization across all SERDES channels. This multi-functionality eliminates the need for dedicated synchronization circuitry, reducing overall component quantity while achieving data coherence across channels.
Data Source
AI summary
In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.