SerDes Transmitter Tap Weighting for Low-Power Pulse Compensation
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Solution Overview
Problem
High-speed serializer/deserializer (SerDes) circuits in integrated circuits face challenges with increasing power dissipation and area requirements due to high data rates, exacerbated by pulse response effects that distort analog signals, making it difficult for receivers to accurately determine digital data from analog pulses.
Innovation Solution
A SerDes transmitter system comprising a digital block and an analog block that generates serialized output pulses using combinations of current bits and history bits, applying tap weightings to reduce redundant data transfer and minimize power consumption, with a focus on using a cursor bit and post-cursor bits to compensate for pulse response effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high data rates are used to increase bandwidth, then data transfer speed is improved, but power dissipation increases
Solution Approach 1:
The patent segments the data transmission process by dividing data into groups of bits that are processed and transmitted together as a unit. This segmentation allows for more efficient use of transmission resources and reduces the overhead associated with individual bit transmission, thereby improving data transfer speed while reducing power consumption per bit transmitted.
Solution Approach 2:
The patent employs periodic transmission of data groups synchronized with clock cycles. By organizing data transmission into periodic groups aligned with clock phases, the system achieves higher effective data rates while allowing power management circuits to optimize power delivery in a periodic manner, reducing overall power dissipation compared to continuous high-speed transmission.
2Productivity
If more SerDes transmitter and receiver lanes are integrated to support increasing bandwidth, then data transfer capability is improved, but chip area increases
Solution Approach 1:
The patent implements a universal data transmission interface that can handle multiple data rates and configurations through a single SerDes lane. By making the transmitter and receiver circuits multi-functional and adaptable to different operating modes, the system achieves increased total bandwidth without proportionally increasing the number of physical lanes, thereby reducing chip area consumption.
Solution Approach 2:
The patent utilizes parameter changes in the data transmission process, such as variable clock phases and adjustable data group sizes, to optimize the performance of existing SerDes lanes. By dynamically adjusting transmission parameters rather than adding more fixed-function lanes, the system increases bandwidth capacity while minimizing additional chip area requirements.
3Speed
If high speed datapaths with multigigahertz clocks are used, then data rate is improved, but power dissipation in circuits increases
Solution Approach 1:
The patent uses periodic clock cycles with multiple phases to drive high-speed data transmission. By organizing data transmission into periodic groups synchronized with multi-phase clocks, the system achieves multigigahertz data rates while allowing power management to optimize energy delivery in a periodic manner, reducing circuit power dissipation compared to continuous high-frequency operation.
Solution Approach 2:
The patent segments data transmission into discrete groups processed during specific clock phases. This segmentation allows high-speed datapaths to operate at multigigahertz frequencies only when data is being transmitted, rather than continuously, thereby achieving high data rates while reducing overall power dissipation in the high-speed circuitry.
4Device complexity
If pulse response effects are not compensated, then circuit complexity is reduced, but data accuracy deteriorates
Solution Approach 1:
The patent applies preliminary compensation for pulse response effects by pre-adjusting data groups before transmission based on expected channel characteristics. By performing this compensation in advance in the digital domain, the system improves data accuracy at the receiver without requiring complex analog compensation circuits, thereby maintaining low circuit complexity while achieving high measurement precision.
Data Source
AI summary
A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.