Ser-Des Test Chip Dynamic Path Selection
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Solution Overview
Problem
Serializer/deserializer (Ser-Des) test chips face limitations in inter-operability data rate range and skew on data pins, restricting performance due to GPIO speed limits and requiring costly and delayed SoC development for fault rectification.
Innovation Solution
The implementation of a Ser-Des test chip with multiple transmit and receive paths, including a bypass path, single data rate (SDR) path, and double data rate (DDR) path, which dynamically adjusts data transfer rates and bus widths based on input/output (I/O) speed limits and available I/O pins, using data sampling techniques and width converters to enhance interoperability and reduce skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the test chip uses GPIO for parallel interface, then the device complexity is reduced, but the inter-operability data rate range is limited by the GPIO speed limit
Solution Approach 1:
The patent implements multiple transmit paths (first transmit path for very low data rates, second transmit path for single data rate, third transmit path for double data rate) that can be dynamically selected based on the required data transfer rate. This dynamic path selection allows the test chip to adapt to different data rate requirements beyond the fixed GPIO speed limit, resolving the contradiction between using simple GPIO interfaces and achieving high data transfer rates with wide adaptability range.
Solution Approach 2:
The patent changes the data transfer parameters by implementing different transmit paths with different data rates. The system can switch between very low data rate mode, single data rate mode, and double data rate mode depending on the testing requirements. This parameter change approach allows the test chip to exceed the GPIO speed limit while maintaining compatibility with standard interfaces.
2Productivity
If the test chip increases data transfer rate beyond I/O speed limit, then the productivity is improved, but the skew on data pins increases
Solution Approach 1:
The patent segments the data transfer function into multiple transmit paths, each optimized for different data rate ranges. By dividing the data transfer task into separate paths (first transmit path for very low data rates, second transmit path for single data rate, third transmit path for double data rate), the system can select the appropriate path that minimizes skew while achieving the required productivity. This segmentation allows high-speed testing without excessive skew by using the third transmit path only when necessary.
3Reliability
If the test chip uses multi-layered structure, then the inter-operability can be verified, but the device complexity increases
Solution Approach 1:
The patent implements a universal test chip structure that can handle multiple data rate requirements (very low data rate, single data rate, double data rate) through a single integrated device. The test chip includes multiple transmit paths and receive paths that can be selectively activated, eliminating the need for separate test chips for different data rates. This multi-functionality approach verifies inter-operability across different protocols (SDR and DDR) while maintaining a single, manageable device structure rather than requiring multiple specialized chips.
Data Source
AI summary
There is provided a method for managing the inter-operability data rate range of serializer/deserializer (Ser-Des) test chips. The method doubles the inter-operability data rate range of the Ser-Des test chip, reduces the skew on data pins, and thereby increases the performance in the inter-operability test of the Ser-Des test chip.