SERDES Time Synchronization via Parallel Interface Timestamping
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Solution Overview
Problem
The 5G communication network requires higher time synchronization precision than 4G networks, particularly in centralized access networks and feed-forward bearer networks, which existing Ethernet 1588 technology fails to meet due to delay jitter affecting timestamp accuracy at the PHY and MAC layer interface.
Innovation Solution
A time synchronization method that searches for a preset synchronization block at the SERDES parallel interface, determines its position and time point, and calculates the timestamp of a PTP packet at the SERDES serial interface using a traffic model, thereby improving synchronization precision without increasing search costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If time synchronization is performed at the PHY and MAC layer interface using PTP packets, then the synchronization mechanism can be implemented, but delay jitter on the path between the reference plane and the physical interface degrades the timestamp accuracy and prevents high-precision synchronization
Solution Approach 1:
The patent introduces a SERDES parallel interface as an intermediary reference plane between the PHY layer and MAC layer. By placing the timestamp reference plane at this intermediate location and using a traffic model to calculate equivalent timestamps at the serial interface, the system avoids the delay jitter problem that occurs when timing at the physical interface, thereby achieving high-precision synchronization without being affected by path delay variations
Solution Approach 2:
The patent replaces the traditional mechanical/timing-based approach of directly timestamping at the physical interface with a computational approach. Instead of measuring time at the PHY/MAC interface subject to jitter, the system uses a traffic model to calculate what the timestamp would be at the SERDES serial interface based on measurements taken at the parallel interface, substituting direct measurement with model-based computation to eliminate jitter effects
2Adaptability or versatility
If the reference plane for timestamp is placed at the PHY and MAC layer interface, then the existing Ethernet 1588 technology can be used, but the delay jitter on the path affects the timestamp and cannot meet the high precision requirements of 5G networks
Solution Approach 1:
The patent adds a new dimension to the timing architecture by introducing the SERDES parallel interface as a separate reference plane distinct from the traditional PHY/MAC interface. This dimensional separation allows the system to maintain compatibility with existing Ethernet 1588 protocols while operating at a higher timing precision level, effectively adding a new layer to the timing hierarchy that resolves the contradiction between compatibility and precision
3Measurement precision
If high-precision time synchronization is required for 5G feed-forward bearer networks, then the synchronization requirements increase to less than plus or minus 10 nanoseconds, but the existing PTP packet processing at PHY and MAC layer cannot achieve this precision due to delay jitter
Solution Approach 1:
The SERDES parallel interface acts as an intermediary reference plane that simplifies the timing architecture. By positioning the timestamp reference at this intermediate point rather than at the complex physical interface, the system achieves high precision while reducing the effective complexity of the timing reference, as the parallel interface provides a more stable and controllable timing environment
Data Source
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AI summary
Provided are a time synchronization method and device, and a storage medium. The method includes that: a synchronized block matching a preset code pattern in a data stream is searched at a SERDES parallel interface; the position of the bit of the synchronized block in the SERDES parallel interface is determined as a first position; a time point when the synchronized block passes through the SERDES parallel interface is determined as a first time point; the synchronized block and a PTP packet in the data stream are searched at an interface between PHY layer and MAC layer, and a distance between the synchronized block and the PTP packet is determined; and a second time point is determined according to the first position, the first time point and the distance, the second time point being the time point when the PTP packet passes through an SERDES serial interface.