SerDes Parallel-Interface Timestamping for Ethernet Sync Accuracy
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Solution Overview
Problem
Current methods for measuring packet timestamps in Ethernet networks face challenges due to non-deterministic latency and difficulty in synchronizing clocks across the MII and MDI interfaces, leading to inaccurate timestamp calculations and synchronization errors.
Innovation Solution
The approach involves generating timestamps at the SerDes interface based on specific bits that represent path data delays, eliminating the need for direct measurement of path data delays and MII timestamps, and using SerDes specific bit timestamps to calculate packet timestamps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If packet timestamps are measured at MII interface, then timestamp calculation can be performed, but non-deterministic latency and synchronization errors occur between MII and MDI interfaces
Solution Approach 1:
The patent introduces SerDes specific bits as intermediary reference points between MII and MDI interfaces. These specific bits traverse the entire path from MII through SerDes to MDI, serving as mediators that carry timing information across the interface boundary. By timestamping these intermediary bits at MDI and back-calculating MII timestamps, the patent eliminates direct MII-MDI synchronization requirements while maintaining accurate packet timing measurement.
2Measurement precision
If path data delay measurement is performed directly, then timestamp calculation can be done, but measurement complexity and synchronization difficulty increase
Solution Approach 1:
The patent creates copies of specific reference bits at multiple points in the data path (at MII and at MDI). By timestamping these bit copies at different locations and using the known relationship between them, the system calculates path data delay without requiring direct measurement apparatus. This copying approach simplifies the measurement system while maintaining high precision through the use of identical reference bit patterns.
3Ease of operation
If MII timestamps are used for packet timing, then timestamping can be performed, but clock synchronization errors between MII and MDI interfaces occur
Solution Approach 1:
Instead of directly timestamping packets at MII and transferring timing information to MDI (which requires clock synchronization), the patent inverts the approach by timestamping at MDI first and then back-calculating the MII timestamp. This inversion eliminates the need for bidirectional clock synchronization between MII and MDI interfaces, as timing information flows in one direction only, from the physically accessible MDI interface back to the logical MII reference point.
Data Source
AI summary
One or more examples relate, generally, to timestamp at a parallel interface of a SerDes for coupling a PHY with a physical transmission medium. In an example, an apparatus includes a SerDes to couple a PHY to a physical transmission medium; a hardware timestamp logic; a bit detector coupled to initiate the hardware timestamp logic at least partially responsive to observing an indicated bit at a parallel interface of the SerDes; and a logic circuit provided at a portion of the PHY, the logic circuit coupled to receive timestamps generated by hardware timestamp logic.