3D SER/DES Die Stacking With TSVs for High-Speed Interconnects

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Solution Overview

Problem

Existing IC packaging methods, particularly for SER/DES devices, face challenges in achieving high-speed data transmission due to inductance and capacitance issues with wirebond connections, making them unsuitable for 3D stacked die packaging, and require spacer materials that increase package height and cost.

Innovation Solution

Implementing Through Silicon Via (TSV) connections within SER/DES blocks to vertically stack dice, eliminating wirebonds and enabling high-speed data transfer with reduced inductance and capacitance, and using redistribution layers (RDL) for alignment and routing, while eliminating the need for spacers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wirebond connections are used for SER/DES devices, then ease of manufacture is improved, but inductance and capacitance increase making high-speed data transmission impossible

Engineering Contradiction:

Improveease of manufactureVSAvoidhigh-speed data transmission capability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent extracts and eliminates the wirebond connections from the packaging system, replacing them with TSV-based direct electrical connections. This removes the source of inductance and capacitance problems while maintaining manufacturability through established TSV fabrication processes.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical wirebond connection system with an integrated TSV electrical connection system. The TSVs provide direct vertical electrical pathways through the substrate, eliminating the need for separate wirebonding operations and their associated parasitic effects.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Quantity of substance

If 3D stacked die packaging is implemented, then device density increases, but wirebond inductance prevents high-speed SER/DES operation

Engineering Contradiction:

Improvedevice densityVSAvoidhigh-speed data transmission

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar 2D packaging to 3D stacked packaging by implementing vertical TSV connections. This allows multiple SER/DES devices to be stacked in the vertical dimension, increasing density while the TSVs provide low-inductance pathways that enable high-speed operation in the stacked configuration.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If spacers are used in stacked die packaging, then alignment is facilitated, but package height and cost increase

Engineering Contradiction:

Improvealignment facilitationVSAvoidpackage height

Core Design Contradiction:

Ease of manufactureVSLength of stationary object

Solution Approach 1:

The patent merges the alignment function into the TSV structure itself and the substrate design, eliminating the need for separate spacer components. The TSV locations and substrate land patterns provide inherent alignment references, reducing package height while maintaining alignment accuracy through integrated design features.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250273553A12.5d/3d system integration

Publication Date: 2025.08.28 BROADPAK CORP

AI summary

Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.