SerDes VCO Current Injection for Low-Jitter PLL Corners
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Solution Overview
Problem
Ring oscillator phase locked loops (PLLs) in serdes devices face challenges in achieving high VCO frequencies across various PVT conditions, leading to increased VCO gain and thermal noise, which complicates the requirement for a large loop capacitor and contributes to jitter in the clock output.
Innovation Solution
Injecting a fixed current into the ring oscillator, proportional to the speed of PVT conditions, reduces VCO gain and thermal noise, and adjusts the loop capacitor size to maintain desired loop bandwidth with peaking of less than 1 dB, using a replica oscillator and current mirror to dynamically adjust the current based on corner conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the VCO operates over a wide frequency range to meet timing requirements, then the VCO gain increases, but the thermal noise contribution of the loop resistor increases and jitter is introduced
Solution Approach 1:
The patent implements dynamic adjustment of the VCO gain through a programmable gain amplifier (PGA) that can be configured based on operating conditions. The PGA gain is controlled by a gain control signal that adjusts the amplification factor dynamically, allowing the system to optimize the balance between frequency range and noise performance. This dynamic adaptation resolves the contradiction by enabling high frequency range when needed while minimizing thermal noise contribution when frequency range is sufficient.
2Speed
If the VCO gain is increased to support high PLL frequencies under slow corner conditions, then the frequency range is extended, but the loop capacitor size must be increased to maintain desired loop bandwidth with peaking less than 1 dB
Solution Approach 1:
The patent changes the gain parameter of the VGA dynamically based on the operating corner conditions. By adjusting the VGA gain according to the PVT corner (fast, nominal, slow), the system can achieve the required PLL frequency without proportionally increasing the loop capacitor size. The gain adjustment compensates for variations in VCO performance across corners, allowing consistent loop bandwidth and peaking characteristics with a fixed or reduced capacitor value.
3Stability of the object's composition
If a large loop capacitor is used to reduce peaking, then the loop bandwidth is maintained, but the device area increases
Solution Approach 1:
The patent uses programmable gain adjustment in the VGA to control loop peaking without requiring large capacitor values. By changing the gain parameter based on operating conditions, the system can achieve the desired peaking characteristics (less than 1 dB) with a smaller loop capacitor, thereby reducing the device area while maintaining stability.
4Adaptability or versatility
If the transistor speed varies under different PVT conditions, then the VCO frequency changes, but the clock quality and jitter performance deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the system detects or estimates the PVT corner conditions and adjusts the VGA gain accordingly. This feedback loop ensures that despite variations in transistor speed under different PVT conditions, the PLL maintains optimal performance with minimal jitter. The gain adjustment compensates for corner-related performance degradation, preserving clock quality across all operating conditions.
Data Source
AI summary
Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region.