SERDES Voltage Reference Generator Settling Time

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Solution Overview

Problem

High-speed parallel data transmission in computing systems is hindered by parasitic effects such as signal noise and impedance mismatch, leading to increased propagation delays and reduced frequency transmission, which are exacerbated by the physical properties of wide communication buses and the inherent non-linear frequency response of serial link channels, causing Intersymbol Interference (ISI).

Innovation Solution

The implementation of a serial data system that adjusts the reference voltage using multiple current sources and resistors to minimize settling time and compensate for ISI, allowing for efficient data transmission by configuring current sources to sink currents based on control signals and data symbols, thereby optimizing the common mode voltage and reducing distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If parallel data transmission is used, then data transmission width is increased, but parasitic effects and signal noise increase leading to reduced frequency transmission

Engineering Contradiction:
Improvedata transmission widthVSAvoidsignal quality
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the wide parallel data bus into multiple narrower serial data lanes. Instead of transmitting all data bits simultaneously over a wide bus that suffers from parasitic effects, the data is segmented into individual bits transmitted sequentially over multiple smaller channels, each with reduced parasitic inductance and capacitance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from spatial parallelism (wide bus) to temporal parallelism (multiple serial lanes). By adding the time dimension to data transmission, the system achieves equivalent or higher throughput through multiple sequential channels rather than a single wide channel, avoiding the parasitic problems of wide-bus parallel transmission.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If serialization is implemented, then parasitic effects are reduced, but Intersymbol Interference increases due to non-linear frequency response

Engineering Contradiction:
Improveparasitic effect reductionVSAvoidIntersymbol Interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements feedback equalization where the receiver detects ISI on incoming serial data and sends correction information back to the transmitter. The transmitter then adjusts its transmission parameters based on this feedback to compensate for the non-linear frequency response and reduce ISI effects.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies preliminary equalization at the transmitter end before data transmission, based on pre-characterized channel response. By anticipating and compensating for ISI effects in advance, the system reduces the impact of non-linear frequency response before the interference occurs during transmission.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If wide buses are used, then data transmission capacity is increased, but area consumption and propagation delays increase

Engineering Contradiction:
Improvedata transmission capacityVSAvoidpropagation delay
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the wide data bus into multiple serial lanes, allowing data to be transmitted through shorter individual paths rather than long parallel traces. This segmentation reduces the propagation delay for each data bit while maintaining overall transmission capacity through parallel processing of multiple lanes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic voltage scaling and clock gating in the serial transmission system. By dynamically adjusting voltage and clock frequencies based on data patterns and channel conditions, the system optimizes propagation delay and energy efficiency while maintaining high data transmission capacity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10778478B2Fast-settling voltage reference generator for SERDES applications
Publication Date: 2020.09.15 ORACLE INT CORP
  • US10778478B2 patent drawing
  • US10778478B2 patent drawing
  • US10778478B2 patent drawing

AI summary

A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was received prior to the particular data symbol.