Dynamic SERDES Link Width Modulation for Power Optimization
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Solution Overview
Problem
High-speed serializer/deserializer (SERDES) links in computer systems consume significant power even when idle, due to the need for continuous transmission of idle/NOP frames and sync frames, which limits power conservation efforts.
Innovation Solution
A method to dynamically modulate the width of SERDES links based on bandwidth demand by adjusting the number of lanes used for data transmission, with a transmitter circuit determining the optimal number of lanes and sending an indicator to the receiver, allowing for efficient power management by reducing or increasing lanes as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SERDES links continuously transmit idle/NOP frames and sync frames to maintain synchronization, then reliable data transmission and clock synchronization are ensured, but power consumption increases significantly during idle periods
Solution Approach 1:
The patent applies dynamics by making the link width adjustable rather than fixed. The system dynamically changes the number of active lanes based on bandwidth demand, transitioning from full-width operation during active data transmission to reduced-width operation during idle periods. This dynamic adaptation allows the system to maintain synchronization reliability when needed while significantly reducing power consumption during idle periods by transmitting fewer sync frames.
Solution Approach 2:
The patent changes the parameter of link width (number of active lanes) to resolve the contradiction. By varying the link width between full width during active transmission and reduced width during idle periods, the system adjusts the number of sync frames transmitted. This parameter change enables the system to maintain sufficient clock synchronization (requiring some sync frames) while reducing overall power consumption by minimizing the number of frames transmitted during idle periods.
2Use of energy by moving object
If low-power states (L0s and L1) are used to conserve power during low bandwidth periods, then power consumption is reduced, but protocol overhead and transition time increase significantly
Solution Approach 1:
Instead of using discrete low-power states with significant transition overhead, the patent implements a dynamic link width modulation mechanism that allows gradual transition between different numbers of active lanes. The system can transition from using all lanes to using fewer lanes (e.g., half-width or quarter-width) without requiring complete state shutdown and restart, thereby reducing transition time while maintaining power savings during low bandwidth periods.
Solution Approach 2:
The system performs preliminary action by preparing the link width change in advance through negotiation between transmitter and receiver. The transmitter signals the intended link width change to the receiver beforehand, allowing both ends to prepare for the transition. This preliminary coordination enables smoother, faster transitions compared to abrupt state changes, reducing the overall transition time penalty.
3Use of energy by moving object
If the number of lanes is dynamically adjusted based on bandwidth demand, then power consumption is optimized, but link width modulation protocol complexity increases
Solution Approach 1:
The patent employs feedback mechanisms where the transmitter and receiver negotiate and confirm the desired link width change. The receiver provides feedback (acknowledgment signals) to confirm receipt and understanding of the link width modulation command. This feedback loop ensures reliable coordination between transmitter and receiver, managing the protocol complexity through structured interaction while enabling dynamic power optimization through lane adjustment.
Data Source
AI summary
The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes.