Serial ADC Data Framing With Embedded Clock and Marker Words
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed analog to digital converter (ADC) systems face challenges in complex routing and high power requirements due to numerous pins in parallel transmission, and inefficiencies in serial transmission, including skewing issues and inadequate error detection/correction in traditional serial interfaces.
Innovation Solution
A high-speed serial ADC system that assembles sample conversion words into data packets with a marker word, using an embedded clock for transmission, which eliminates the need for separate clock pins, reduces skewing, and incorporates robust real-time error checking/correction, achieving efficiency greater than 87% by trading off marker size and error bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parallel transmission is used, then implementation is simple, but the number of interconnect lines increases requiring more space, complex routing, and more power
Solution Approach 1:
The parallel data bus is segmented into multiple serial channels, each carrying a portion of the data. This segmentation reduces the number of interconnect lines required while maintaining the overall data transmission capability through parallel processing of multiple serial streams
Solution Approach 2:
The patent transitions from a single-plane parallel architecture to a multi-dimensional architecture combining serial transmission with time-division multiplexing and spatial distribution of multiple channels, effectively adding temporal and spatial dimensions to the data transmission approach
2Device complexity
If serial transmission is used, then the number of interconnect lines is reduced, but the data rate per line must be much higher and implementation becomes more complex
Solution Approach 1:
The high data rate requirement is segmented across multiple serial channels, allowing each individual channel to operate at a lower, more manageable data rate while the aggregate throughput maintains the required performance level
Solution Approach 2:
Multiple serial channels are merged at the receiver end to reconstruct the complete data stream, combining the output of several lower-speed channels to achieve the equivalent throughput of a single high-speed channel while reducing per-line speed requirements
3Reliability
If traditional serial interface with separate clock pin is used, then data transmission is achieved, but skewing issues occur between clock and data and clock pin requirements increase
Solution Approach 1:
The clock signal is merged with the data stream by embedding it within the serialized data itself, eliminating the need for separate clock pins and the associated skewing problems between independent clock and data paths
Solution Approach 2:
A marker word serves as an intermediary that carries timing and synchronization information within the data stream, enabling the receiver to recover clock timing without requiring a separate physical clock connection
4Device complexity
If JEDEC JESD204 serial interface is used, then clock pins are eliminated, but the 8B/10B encoding scheme results in maximum ideal efficiency of only 80% and error checking is not sufficiently robust
Solution Approach 1:
The encoding scheme parameters are changed from the standard 8B/10B format to a customized encoding that achieves better than 8B/10B efficiency while maintaining clock recovery capability, optimizing the balance between overhead and data throughput
Solution Approach 2:
A robust feedback mechanism is implemented where the receiver detects errors in the incoming data stream and sends acknowledgment signals back to the transmitter, enabling retransmission of erroneous data and ensuring reliable delivery beyond what standard 8B/10B error checking provides
Data Source
AI summary
A high speed transmission system includes at least one transmitter; a buffer circuit for assembling into a data packet in parallel a number of sample conversion words from said transmitter; a marker circuit for adding a marker word to said data packet for framing said data packet; and a serializer circuit for serializing said data packet either before or after said marker word is added, with an embedded clock for transmission.