Serial Multi-Stage Arbitration Circuit for Equalized Bus Usage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In information processing apparatuses, centralized arbitration schemes lead to increased circuit size and delay due to concentration of arbitration participation signals, making it difficult to equalize bus usage ratios among sources effectively.
Innovation Solution
Implementing a serial multi-stage arbitration scheme with multiple selection circuits connected in series, where each circuit receives data and source identifiers to select and transfer packets based on priority information, updating priorities to ensure equal bus usage among all sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized arbitration scheme is used, then arbitration can be performed for all sources, but the circuit size increases and arbitration delay increases due to concentration of arbitration participation signals
Solution Approach 1:
The patent divides the centralized arbitration function into multiple distributed selection circuits (first selection circuit, second selection circuit, etc.), each handling arbitration for a subset of sources. This segmentation reduces the circuit size of individual arbitration units while maintaining overall arbitration capability across all sources, directly resolving the contradiction between circuit size and arbitration efficiency.
2Adaptability or versatility
If the number of sources increases, then more data can be processed, but arbitration participation signals concentrate on a single point resulting in increased circuit size
Solution Approach 1:
The patent segments the arbitration function across multiple selection circuits, where each circuit handles a portion of the sources. This allows the system to accommodate an increasing number of sources without proportionally increasing the circuit size of individual arbitration units, as the arbitration load is distributed across multiple smaller circuits.
Solution Approach 2:
The patent introduces a multi-dimensional arbitration structure with multiple stages (first selection circuit, second selection circuit, etc.), transforming the single-point centralized arbitration into a distributed multi-stage architecture. This dimensional change allows the system to scale with more sources while maintaining manageable circuit sizes at each stage.
3Ease of operation
If genuine LRU scheme is used for arbitration, then arbitration can be performed, but arbitration participation signals concentrate on a single point with increase in number of sources
Solution Approach 1:
The patent segments the LRU arbitration function across multiple selection circuits, with each circuit implementing LRU arbitration for its subset of sources. This distribution of the LRU function prevents signal concentration at a single point while maintaining the ease of operation of LRU-based arbitration, resolving the contradiction between operational simplicity and circuit complexity.
Data Source
AI summary
An arithmetic processing apparatus includes multiple selection circuits that are connected in series, wherein at least one selection circuit, the at least one selection circuit being served as a first selection circuit, includes a selection unit that selects a first input unit from two or more input units each receiving, from a source or a selection circuit in a previous stage, data and an identifier of a sender of the data; based on the two or more identifiers, and priority information indicating respective priorities for multiple sources connected to: a selection circuit upstream to the first selection circuit; and the first selection circuit; an update unit that updates, in the priority information, a priority for a first source indicated by a first identifier being received by the first input unit; and a transfer unit that transfers data and the first identifier passed through the first input unit, to a destination.