Serial Interface Baud Clock Modulation for Precise Bit Rates
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Solution Overview
Problem
In microcomputers, achieving a bit rate close to a required rate during serial communication is challenging due to variations in operation clock frequencies, leading to bit rate errors and difficulties in adjusting communication speeds without additional resources or wiring.
Innovation Solution
A semiconductor device with a serial communication interface that includes a baud rate generator and a bit rate modulator, which partially masks the operation clock to generate a basic clock, allowing for flexible adjustment of bit rates regardless of the operation clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the operation clock frequency is increased to enable finer bit rate adjustment, then the bit rate precision is improved, but the communication speed decreases
Solution Approach 1:
The patent segments the operation clock into multiple divided clocks with different division ratios. The baud rate generator selects and combines these divided clocks to create the basic clock, enabling fine bit rate adjustment without increasing the overall operation clock frequency. This segmentation allows precise bit rate control while maintaining high communication speed.
Solution Approach 2:
The patent dynamically selects different divided clocks based on the required bit rate. The baud rate generator can switch between different clock division ratios (e.g., 1/2, 1/4, 1/8, 1/16) to optimize the basic clock frequency for each communication scenario, achieving both precision and speed adaptability.
2Use of energy by moving object
If the operation clock frequency is decreased to maintain communication speed, then the energy consumption is reduced, but the bit rate adjustment precision deteriorates
Solution Approach 1:
By segmenting the operation clock into multiple divided clocks, the system can achieve fine bit rate adjustment with a lower operation clock frequency. The baud rate generator combines divided clocks with different ratios to create the basic clock, maintaining adjustment precision while reducing energy consumption.
Solution Approach 2:
The patent changes the division ratios of the clocks rather than changing the operation clock frequency itself. By adjusting the division ratios (e.g., switching between 1/2, 1/4, 1/8, 1/16), the system achieves bit rate precision without increasing the operation clock frequency, thus maintaining low energy consumption.
3Adaptability or versatility
If additional wiring or resources are added to achieve arbitrary bit rate combinations, then the bit rate flexibility is improved, but the device complexity increases
Solution Approach 1:
The patent creates a universal basic clock generation mechanism that can produce multiple bit rates using the same operation clock and divided clocks. The baud rate generator serves multiple functions by selecting different combinations of divided clocks, achieving arbitrary bit rate combinations without additional wiring or resources.
Solution Approach 2:
The system uses its existing operation clock and divided clocks to generate the basic clock for any required bit rate. The baud rate generator self-adjusts by selecting appropriate divided clock combinations, eliminating the need for external resources or additional wiring to achieve bit rate flexibility.
4Measurement precision
If the count value of measuring basic clocks is increased to achieve finer bit rate adjustment, then the bit rate precision is improved, but the communication overhead increases
Solution Approach 1:
The patent dynamically adjusts the division ratios of the clocks to achieve the desired bit rate precision. By selecting appropriate divided clocks (e.g., switching between 1/2, 1/4, 1/8, 1/16 ratios), the system achieves fine bit rate adjustment without increasing the count value or communication overhead.
Data Source
AI summary
Serial communication with a bit rate close to a required bit rate can be performed, regardless of the frequency of an operation clock.A semiconductor device includes a serial communication interface that operates according to a certain operation clock. The serial communication interface is provided with a baud rate generator that generates a basic clock for counting the operation clock to define the unit transfer time based on the count, and a transmission/reception controller for performing control of transmission and reception according to the generated basic clock. Further, the serial communication interface is provided with a bit rate modulator capable of realizing a desired bit rate by partially masking supply of the operation clock to the baud rate generator, and thereby serial communication with a bit rate close to a required bit rate is realized.