Serial Interface BIST with Start Symbol Latency Compensation
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Solution Overview
Problem
Conventional built-in self test circuits for serial interface devices, such as USB 3.0 and PCI Express, face challenges in accurately testing due to unpredictable loopback latency and phase jitter, which restricts the storage capacity of pattern registers and affects test accuracy.
Innovation Solution
A built-in self test circuit that includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit, where a second test pattern identical to the first is generated upon detecting a starting symbol in the test result pattern, allowing for accurate comparison and compensation of loopback latency without requiring large storage for latency estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the storage capacity of the pattern register is increased to compensate for unpredictable loopback latency, then test accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by detecting the starting symbol in advance within the test result pattern. This early detection enables the system to know when the loopback latency has been completed, allowing accurate comparison without requiring excessive storage capacity to cover unpredictable latency periods.
Solution Approach 2:
The patent implements feedback through the symbol detector that monitors the test result pattern for the starting symbol. This feedback mechanism provides real-time information about loopback completion, enabling dynamic adjustment of the comparison timing and eliminating the need for oversized pattern registers.
2Reliability
If a large pattern register is used to accommodate variable loopback latency, then test reliability is improved, but the device occupies more area and resources
Solution Approach 1:
By detecting the starting symbol in advance, the system performs preliminary identification of loopback completion. This allows the pattern register to be sized appropriately for actual latency requirements rather than worst-case scenarios, maintaining reliability while reducing area.
Solution Approach 2:
The patent changes the parameter of pattern register storage capacity by using symbol detection to dynamically determine when comparison should occur. This parameter change allows the system to achieve high reliability with smaller, more area-efficient storage resources.
3Ease of manufacture
If the pattern register storage capacity is restricted to reduce device complexity, then ease of manufacture is improved, but test accuracy deteriorates when loopback latency is great
Solution Approach 1:
The symbol detector provides feedback about loopback completion status, enabling the comparison unit to perform accurate comparisons even with restricted pattern register capacity. The feedback mechanism ensures that comparison occurs at the correct time regardless of latency magnitude.
Solution Approach 2:
The patent introduces dynamics by making the comparison timing adaptive rather than fixed. The system dynamically adjusts when comparison occurs based on real-time detection of the starting symbol, allowing accurate testing with smaller pattern registers suitable for ease of manufacture.
4Device complexity
If conventional BIST circuit is used without symbol detection, then device complexity is reduced, but phase jitter causes errors in pattern comparison
Solution Approach 1:
The symbol detector introduces a feedback mechanism that monitors the test result pattern for the starting symbol. This feedback synchronizes the comparison process with the actual arrival of valid data, compensating for phase jitter without requiring complex circuitry.
Solution Approach 2:
The starting symbol acts as an intermediary that mediates between the variable loopback latency and the pattern comparison process. By detecting this intermediary signal, the system can synchronize comparisons and eliminate phase jitter errors without adding significant circuit complexity.
Data Source
AI summary
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.