Serial Buffer Out-of-Order Response Handling

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Solution Overview

Problem

Conventional serial buffers experience head of line blocking due to their inability to process response packets out of order, leading to slow processing and inefficiencies in handling request and response packets in sRIO systems.

Innovation Solution

A serial buffer is designed to support split request/response transactions with out of order responses by using a buffer memory that stores copies of request packets and assigns unique transaction IDs, allowing responses to be processed in a different order, with a request timeout mechanism to ensure packet delivery by re-sending packets if responses are not received within a certain time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional serial buffer processes response packets in the same order as request packets are transmitted, then the processing order is simple and straightforward, but head of line blocking occurs and processing speed decreases

Engineering Contradiction:
Improveprocessing speedVSAvoidbuffer structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The buffer memory is segmented into multiple independently addressable storage locations, each capable of holding a request packet and its corresponding response packet. This segmentation allows the buffer to store and retrieve packets in any order without head of line blocking, as each segment can be accessed independently. The segmentation resolves the contradiction by enabling faster processing (improving speed) while using a structured memory organization (managing complexity through regular addressing patterns).

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A transaction identifier field is introduced as an intermediary mechanism to associate response packets with their corresponding request packets. This identifier allows the buffer to match responses to requests regardless of processing order, enabling out-of-order response handling without losing packet correspondence. The intermediary resolves the contradiction by enabling flexible processing (improving speed) while maintaining clear packet relationships (managing complexity through identifier matching).

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If the serial buffer waits for response packets in sequential order, then packet correspondence is easily maintained, but processing time increases due to head of line blocking

Engineering Contradiction:
Improveprocessing timeVSAvoidpacket tracking complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The buffer pre-allocates storage locations for request and response packets using a systematic addressing scheme based on transaction identifiers. This preliminary organization allows packets to be stored and retrieved in any order without requiring complex real-time tracking. The preliminary action resolves the contradiction by enabling faster processing (reducing loss of time) while using predetermined memory addressing (managing packet tracking complexity through pre-established patterns).

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer stores copies of both request packets and their corresponding response packets in dedicated memory locations. This copying approach allows the system to maintain multiple representations of packet data, enabling flexible access patterns where responses can be processed independently of request transmission order. The copying resolves the contradiction by enabling parallel access (reducing processing time) while maintaining data integrity through redundant storage (managing complexity through copy management).

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If the serial buffer uses a simple FIFO structure for packet processing, then the buffer structure is simple, but out of order response packets cannot be processed efficiently

Engineering Contradiction:
Improveresponse processing flexibilityVSAvoidmemory addressing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The buffer transitions from a static FIFO structure to a dynamic random access memory structure where packets can be accessed in any order based on their transaction identifiers. This dynamic addressing allows the buffer to adapt to out-of-order responses by directly accessing the appropriate memory location regardless of arrival sequence. The dynamics resolves the contradiction by enabling flexible processing (improving adaptability) while using regular memory addressing patterns (managing complexity through standardized access methods).

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8312241B2Serial buffer to support request packets with out of order response packets
Publication Date: 2012.11.13 AXIRO SEMICONDUCTOR INC
  • US8312241B2 patent drawing
  • US8312241B2 patent drawing
  • US8312241B2 patent drawing

AI summary

Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.