Serial Bus Node Auto-Addressing with Adaptive Shunt Current
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Solution Overview
Problem
Existing serial data bus systems, particularly LIN bus systems, face limitations in addressing a large number of bus nodes due to voltage drop constraints, require small shunt resistor values to minimize losses, and need to operate with negative ground offsets while maintaining a high addressing current within a maximum bus current limit of 40mA, which is challenging for self-test capabilities and EMC behavior.
Innovation Solution
The method involves configuring addressable bus nodes to adapt the addressing current from zero, using a current measurement circuit with a resistor, and a control unit to receive addresses from a bus master, with a maximum current that triggers fault conditions based on the number of connected bus nodes, allowing for a chain reaction to identify the last bus node and assign addresses efficiently, while deactivating addressing currents to prevent overload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each bus node introduces a defined current into the bus for auto-addressing, then the number of addressable bus nodes is limited, but the addressing capability is enabled
Solution Approach 1:
The patent applies dynamics by making the addressing current adaptive rather than constant. Each bus node dynamically adjusts its addressing current based on the number of nodes already addressed, allowing the system to scale to a larger number of nodes while maintaining proper voltage levels for identification.
2Loss of energy
If the resistance of the bus shunt is made as small as possible to minimize losses, then the voltage drop for addressing is reduced, but the addressing current must be increased
Solution Approach 1:
The patent changes the parameter of addressing current from a fixed value to an adaptive value that varies depending on the bus configuration and number of nodes. This allows the system to maintain low shunt resistance while adjusting the addressing current to achieve sufficient voltage drop for proper node identification.
3Measurement precision
If the addressing current is increased to maximize the level across the bus shunt, then the addressing signal strength is improved, but the total current drawn by the bus master exceeds the maximum limit
Solution Approach 1:
The patent segments the addressing current contribution among multiple bus nodes rather than having one node provide the entire addressing current. Each node contributes a portion of the total addressing current, which allows the system to achieve sufficient signal level across the shunt while keeping the total current drawn by the bus master within the 40mA limit.
4Quantity of substance
If the addressing current is increased continuously or in steps to address many bus nodes, then more nodes can be addressed, but the rise time becomes very long
Solution Approach 1:
The patent implements periodic action by using a systematic sequence where bus nodes are addressed in a specific order with periodic initialization runs. The addressing process is structured in cycles where nodes are identified and removed from the addressing pool, allowing efficient progression through multiple nodes without excessive rise time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient address assignment for a large number of bus nodes, reduces shunt resistor resistance, enhances self-test capabilities, and improves EMC behavior by managing addressing currents to prevent bus master overload and ensure correct addressing.
Implementation Method 1
the electrical resistance of the bus shunt should be as small as possible
Implementation Method 2
each bus node introduces a defined current into the bus as part of the auto-addressing. In the one-wire data bus, shunt resistors are inserted in each addressing bus node, at which these currents cause a voltage drop on their way to the bus master
Data Source
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AI summary
The invention relates to a bus node capable of carrying out a method according to the invention for assigning bus addresses to bus nodes of a serial data bus system. The method for assigning bus addresses to bus nodes of a serial data bus system is carried out using bus shunt resistors (R2) in the individual bus nodes (SL1, SL2, SL3) of the data bus system during an assignment period. After carrying out the method for assigning bus addresses to the bus nodes of the serial data bus system during the assignment period, an operating period follows. The bus node includes such a bus shunt resistor (R2). The bus node is characterized by a bus shunt bypass switch (S4) which is open before a bus address is assigned to the bus node during the assignment period and which is closed after a bus address is assigned to the bus node during the assignment period and which remains closed during the operating period.