Serial Bus Subscriber Station With Edge-Timed Bit-Rate Switching
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Solution Overview
Problem
The high bit rate ratio and pulse-width modulation (PWM) encoding/decoding in CAN XL bus systems cause phase errors at receiving nodes, leading to incorrect bit rate switching and reduced data transmission reliability, especially in vehicles with autonomous systems requiring high data rates and robust communication.
Innovation Solution
A subscriber station for a serial bus system with a communication control device that generates a frame with a field having a predetermined length between rising and falling edges to ensure correct sampling of the first bit in the second communication phase, allowing reliable bit rate switching despite phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PWM encoding/decoding is used for signaling operating mode changes, then the transceiver can switch between different bit rates, but a time delay is introduced that causes phase errors at receiving nodes
Solution Approach 1:
The invention inserts a synchronization field before the data phase to preliminarily establish timing reference at receiving nodes. This field contains a known bit pattern that allows receivers to resynchronize their sampling clocks before the actual data transmission begins, thereby compensating for the phase delay introduced by PWM decoding and preventing sampling errors during the high-speed data phase
Solution Approach 2:
The synchronization field acts as an intermediary element between the arbitration phase and the data phase. It provides a transition buffer that allows receiving nodes to adjust their timing without affecting the arbitration process or the subsequent data transmission, mediating the timing mismatch caused by PWM encoding/decoding
2Productivity
If a high bit rate ratio is used between arbitration phase and data phase, then data transmission speed is improved, but phase errors increase causing incorrect bit sampling
Solution Approach 1:
The synchronization field is inserted preliminarily before the high-speed data phase to prepare receiving nodes for the upcoming bit rate change. By providing a known pattern at the transition point, it enables receivers to resynchronize their sampling clocks before the high-speed data transmission begins, ensuring accurate sampling despite the high bit rate ratio
Solution Approach 2:
The invention changes the timing parameters dynamically by inserting the synchronization field with a predetermined length that is specifically designed to accommodate the phase error introduced by the high bit rate ratio. This parameter adjustment ensures that the sampling window for the first data bit falls within the correct time window even with significant clock tolerance variations
3Adaptability or versatility
If clock tolerance is allowed for flexibility, then system adaptability is improved, but phase error increases leading to invalid frames
Solution Approach 1:
The synchronization field provides a preliminary timing reference that allows receiving nodes to resynchronize their clocks before data transmission. This preliminary action compensates for clock tolerance variations, ensuring that even with flexible clock frequencies, the sampling of critical bits remains accurate and frames remain valid
Solution Approach 2:
The known bit pattern in the synchronization field provides feedback information to receiving nodes, allowing them to detect and correct timing offsets. By comparing the received pattern with the expected pattern, receivers can adjust their sampling timing to account for clock tolerance, maintaining frame validity despite frequency variations
Data Source
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AI summary
The invention relates to a subscriber station (10; 30) for a serial bus system (1) and to a method for communication in a serial bus system (1). The subscriber station (10; 30) has a communication control unit (11; 31) for controlling the communication of the subscriber station (10; 20; 30) with at least one other subscriber station (10; 20; 30) of the bus system (1) and for generating a transmission signal (TXD), such that, for a message (45) that is exchanged between subscriber stations (10; 20; 30) of the bus system (1), the bit time (t_bt1) of a signal sent to the bus (40) in a first communication phase (451) can differ from a bit time (t_bt2) of a signal sent in the second communication phase (452), wherein the communication control unit (11; 31) is designed to generate the transmission signal (TxD) according to a frame (450) and to introduce a field (ADS) with an increasing edge and a subsequent decreasing edge into the frame (450) in order to transfer from the first communication phase (451) into the second communication phase (452), and wherein the field (ADS) has a predetermined length between the increasing edge and the subsequent decreasing edge, such that a sampling time (t1), at which a communication control unit (21; 31;11) of the at least one other subscriber station (10; 20; 30) of the bus system (1) samples the first bit (DH1) of the second communication phase (452), is arranged between the increasing edge and the subsequent decreasing edge.