Serial Bus Receive Clock Calibration for Interrupt Operations
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Solution Overview
Problem
Traditional camera systems using the Camera Control Interface (CCI) protocol over an Inter-Integrated Circuit (I2C) bus require dedicated interrupt pins for each slave node, leading to increased device cost and complexity due to the need for multiple pins.
Innovation Solution
A method is described where a master device generates a clock signal on the SCL line, calibrates a delay based on the time between clock edges and data transitions on the SDA line, and uses this calibrated clock to receive data, allowing in-band interrupt operations without the need for dedicated interrupt lines or pins, thereby reducing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated interrupt pins are used for each slave node, then interrupt operations can be performed reliably, but device cost and complexity increase due to the large number of pins required
Solution Approach 1:
The patent combines the interrupt request function with the existing SDA data line by using a dedicated time slot within the I2C communication protocol. Slave nodes send interrupt requests by asserting the SDA line during specific periods when the master is not transmitting data, thereby merging the interrupt functionality into the existing two-wire interface without requiring additional pins.
Solution Approach 2:
The SDA line is designed to serve multiple functions: it acts as a bidirectional data line for normal I2C communication and simultaneously serves as an interrupt request line for slave nodes. This multi-functionality eliminates the need for separate dedicated interrupt pins while maintaining reliable interrupt operations.
2Ease of operation
If separate interrupt lines are used for each slave node, then interrupt signaling is straightforward, but hardware cost increases due to increased pin count
Solution Approach 1:
The patent merges the interrupt request function with the existing SDA data line by using a dedicated time slot within the I2C communication protocol. Slave nodes send interrupt requests by asserting the SDA line during specific periods when the master is not transmitting data, thereby merging the interrupt functionality into the existing two-wire interface without requiring additional pins.
Solution Approach 2:
The interrupt mechanism operates periodically within the I2C protocol framework. The master node allocates specific time periods during which slave nodes can assert interrupt requests on the SDA line, creating a structured periodic interrupt scheme that maintains simplicity while reducing hardware requirements.
3Device complexity
If a shared control data bus is used without dedicated interrupt lines, then hardware complexity is reduced, but timing synchronization between clock edges and data transitions becomes more difficult
Solution Approach 1:
The master node performs preliminary actions by establishing a known timing framework through regular clock signaling on the SCL line. Before slave nodes assert interrupt requests on the SDA line, the master has already set up the timing context, allowing the slave's interrupt assertion to be precisely timed relative to the master's clock edges.
Solution Approach 2:
The master node continuously monitors the SDA line for interrupt assertions and uses the SCL clock line to provide timing feedback. When an interrupt is detected, the master can acknowledge it at the next appropriate clock edge, creating a feedback loop that maintains precise timing synchronization between the shared bus components.
Data Source
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AI summary
Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock.