Serial Bus Clock Edge Trigger for Low Latency Control
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Solution Overview
Problem
Mobile communication devices face increased latency issues on shared serial buses, particularly when multiple devices are concurrently active, leading to dropped packets and session timeouts, which hinder high-priority and time-critical data transmission.
Innovation Solution
The method involves receiving configuration information over a serial bus and using clock pulses to reconfigure devices, with triggers activated based on specific edges of the clock pulses, allowing for efficient data transfer without increasing bus clock frequency or modifying encoding, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple devices are concurrently active on a shared serial bus, then device functionality and communication capability are improved, but latency increases and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-configuring devices with configuration information that includes trigger activation information before actual data transmission. The trigger is set to activate automatically upon detecting a specific clock pulse edge, eliminating the need for additional trigger commands during time-critical operations. This preliminary setup reduces latency while maintaining multi-device functionality on the shared serial bus.
2Adaptability or versatility
If multiple devices are concurrently active on a shared serial bus, then device functionality is improved, but reliability deteriorates due to dropped packets and session timeouts
Solution Approach 1:
The patent pre-configures triggers with activation information and specific edge detection conditions before transmission. This preliminary action ensures that time-critical data transmission is immediately executed when conditions are met, reducing the window for transmission errors and improving reliability in multi-device concurrent operations.
3Ease of operation
If configuration information is received and processed through traditional methods, then device reconfiguration is achieved, but latency increases due to additional trigger commands and clock-cycle overhead
Solution Approach 1:
The patent embeds trigger activation information within the configuration information itself, allowing the trigger to be automatically activated upon detecting a specific clock pulse edge. This eliminates the need for separate trigger commands and reduces clock-cycle overhead, achieving fast device reconfiguration with minimal latency.
Solution Approach 2:
The patent merges the configuration information and trigger activation information into a single transmission package. By combining these functions, the system eliminates redundant communication steps and reduces the overall time required for device reconfiguration while maintaining ease of operation.
4Productivity
If bus clock frequency is increased to improve data rates, then transmission speed is improved, but power consumption and system complexity increase
Solution Approach 1:
The patent utilizes specific edges of clock pulses as periodic triggers to activate pre-configured triggers. This approach allows efficient data transfer by synchronizing operations with existing clock edges rather than increasing clock frequency, thereby improving data rate handling without increasing power consumption.
5Productivity
If encoding of transmitted data is modified to improve data rates, then transmission efficiency is improved, but device compatibility and system complexity increase
Solution Approach 1:
The patent achieves improved data rates by utilizing periodic clock pulse edges to trigger pre-configured operations. This method improves transmission efficiency without modifying data encoding, thereby maintaining device compatibility and avoiding increased system complexity.
Data Source
AI summary
Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.