Serial Bus Clock Phasing for Low-Power Secondary Nodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wired communication systems, such as SPI or I2C buses, consume excessive power due to the need for devices to constantly load and unload data wires to specific potentials, and the clock signal is often generated by the secondary device, increasing power consumption.
Innovation Solution
A Zero-Power bus system where the primary device generates a clock signal defining four phases for data transmission, allowing the secondary device to remain in a high impedance state during most phases, reducing power consumption by eliminating the need to load the data wire to a potential for both data and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the secondary device generates the clock signal in traditional wired communication systems, then the data transmission can be synchronized, but the power consumption increases due to the need to constantly load and unload data wires to specific potentials
Solution Approach 1:
The patent inverts the traditional role assignment by making the primary device generate the clock signal instead of the secondary device. This inversion allows the secondary device to remain in high impedance state during clock phases, eliminating the need to charge/discharge capacitance during clock signal generation, thereby significantly reducing power consumption while maintaining synchronization through the primary device's clock output
Solution Approach 2:
The patent implements periodic action by dividing the data transmission into distinct phases (first phase for clock signal, second phase for data transmission) with the secondary device switching between active and high impedance states periodically. This periodic switching allows the secondary device to minimize its active engagement with the data wire, reducing overall power consumption while ensuring proper signal transmission during designated phases
2Reliability
If the secondary device constantly loads and unloads data wires to specific potentials for data transmission, then reliable data communication is achieved, but excessive power is consumed
Solution Approach 1:
The patent applies periodic action by structuring the communication protocol into distinct phases where the secondary device actively drives the data wire only during the second phase (data transmission phase) and remains in high impedance state during the first phase (clock phase). This periodic engagement ensures reliable data communication when needed while minimizing energy consumption by avoiding continuous loading and unloading of the data wire
Solution Approach 2:
The patent implements self-service by having the primary device handle the clock signal generation and initial data wire loading, while the secondary device only needs to perform minimal actions (driving data during its designated phase) and otherwise remain passive. This division of labor allows the secondary device to achieve reliable communication with minimal energy expenditure by leveraging the primary device's active management of the communication bus
Data Source
AI summary
The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.