Serial Bus Frame Formatting With Control Bits for Lower Power
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Solution Overview
Problem
Existing serial bus communication systems, such as SPI and I2C, face challenges in reducing power consumption and optimizing data transmission efficiency due to fixed frame formats and reliance on secondary devices to provide clock signals.
Innovation Solution
A serial bus system with a primary device providing a clock signal and control bits, where the format of each frame is determined by the number of control bits, allowing for implicit indication of device and register addresses, and optimizing phases of bit transmission to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a fixed frame format is used in serial bus communication, then device complexity is reduced and ease of operation is improved, but power consumption increases and data transmission efficiency deteriorates
Solution Approach 1:
The patent implements dynamic frame formats where the structure and length of frames adapt based on the number of control bits. This allows the communication protocol to optimize each transmission by including only necessary fields (device address, register address, data) rather than always using a fixed comprehensive format, thereby reducing power consumption while managing complexity through controlled adaptability.
Solution Approach 2:
The patent changes the parameter of frame format structure based on the number of control bits. When control bits indicate implicit addressing mode, the frame format excludes explicit address fields, reducing the total number of bits transmitted and lowering power consumption. The system dynamically adjusts frame parameters (length, content) rather than maintaining a static format.
2Use of energy by moving object
If explicit address fields are included in every frame, then measurement precision of device identification is improved, but the number of bits transmitted increases and power consumption rises
Solution Approach 1:
The patent extracts the address indication function from explicit address fields and implements it through implicit methods using control bits. Instead of always including device address and register address fields in every frame, the system uses control bits to indicate whether addresses are implicitly understood, removing unnecessary data transmission and reducing power consumption while maintaining accurate device identification.
Solution Approach 2:
The system uses self-service addressing where the receiver device automatically identifies itself or its register based on control bit patterns without needing explicit address fields in every frame. The control bits serve as self-descriptive indicators that enable the receiving device to understand which device and register the data pertains to, eliminating redundant address information.
3Adaptability or versatility
If control bits are used to determine frame format, then adaptability of the communication protocol is improved, but device complexity increases
Solution Approach 1:
The patent segments the frame into distinct functional parts with control bits at the beginning that determine the interpretation of subsequent fields. This segmentation allows the system to adapt the meaning and presence of different frame portions (address fields, data fields) based on control bit values, providing high adaptability while maintaining relatively simple processing through clear structural division.
Data Source
AI summary
In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.