Serial Bus Frame Control for Low-Power Register Addressing
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Solution Overview
Problem
Existing serial buses, such as SPI and I2C, face limitations in reducing power consumption and efficiency during data transmission, particularly in determining frame formats and addressing register operations.
Innovation Solution
A serial bus system with a primary device providing a clock signal and control bits, where the format of each frame is determined by the number of control bits, allowing for adaptive frame structure to indicate device and register addresses, and optimizing data transmission phases to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a fixed frame format is used for data transmission on serial buses, then device complexity is reduced and ease of operation is improved, but power consumption increases due to transmission of unnecessary control bits
Solution Approach 1:
The patent implements dynamic frame formats where the structure of each frame is determined by control bits that specify the number of data bits, device address bits, and register address bits. This allows the frame format to adapt to different transmission needs, sending only necessary control bits and reducing power consumption while maintaining flexibility in device communication.
Solution Approach 2:
The patent changes the parameters of the frame format dynamically by using control bits to define the length and structure of data, device address, and register address fields. This parameter adaptation allows the system to optimize power consumption by transmitting minimal necessary information while maintaining the ability to communicate with multiple devices and registers.
2Reliability
If control bits are transmitted for every data transmission, then reliability of data transmission is improved, but loss of time increases due to overhead of control bit transmission
Solution Approach 1:
The patent applies partial action by transmitting control bits only when necessary to define the frame structure. The control bits specify the number of data bits, device address bits, and register address bits, allowing the system to send minimal necessary control information rather than fixed overhead, thus reducing transmission time while maintaining reliability.
3Ease of operation
If explicit device address and register address fields are included in every frame, then ease of operation is improved, but quantity of transmitted data increases leading to higher power consumption
Solution Approach 1:
The patent dynamically changes the parameters of address fields by using control bits to specify the number of device address bits and register address bits in each frame. This allows the system to transmit only the necessary number of address bits for the current operation, reducing the quantity of transmitted data and power consumption while maintaining ease of operation through explicit addressing when needed.
4Adaptability or versatility
If fixed number of data bits per frame is used, then device complexity is reduced, but adaptability decreases when varying data lengths are needed
Solution Approach 1:
The patent implements dynamic data bit lengths by using control bits to specify the number of data bits in each frame. This allows the frame structure to adapt to varying data length requirements, improving versatility while the standardized control bit format maintains manageable device complexity through consistent parsing logic.
Data Source
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AI summary
The present disclosure relates to a system comprising: a serial bus having a data wire and a clock wire; a primary device connected to the bus and configured to provide a clock signal on the clock wire and to provide control bits on the serial bus; and one or a plurality of secondary devices each connected to the bus, a format of each frame (F2) transmitted on the serial bus is determined by a number (N, P, Q) of control bits (ctrl) at at least one location (L2, L3, L4) of said frame.