Serial Bus Gateway Direct Data Transfer Architecture
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Solution Overview
Problem
Conventional gateways for data transfer between serial buses experience long latency times and high CPU load, limiting data transfer speed and efficiency.
Innovation Solution
A gateway with multiple communication modules and a bus master that controls word-based data transfer via an internal data bus, using separate source and destination address buses to enable direct, unbuffered data transfer between communication modules within a single clock cycle, reducing latency and CPU load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data transfer is performed via CPU interface with buffering, then data transfer can be managed through standard processing, but latency increases and data transfer speed decreases
Solution Approach 1:
The patent extracts the data transfer function from the CPU interface by introducing a dedicated direct data transfer mechanism between communication modules. This allows data to be transferred without passing through the CPU's buffered processing path, thereby reducing latency and increasing transfer speed while maintaining manageable control through the simplified direct transfer architecture.
2Adaptability or versatility
If multiple independent communication modules are used with CPU interface, then connectivity between different buses is achieved, but CPU load increases due to data exchange through processor interface
Solution Approach 1:
The patent extracts the data transfer burden from the CPU by implementing direct data transfer between communication modules. Each communication module maintains its own interface to different buses, and data is exchanged directly between modules without requiring CPU intervention for data handling, thus reducing CPU load while preserving multi-bus connectivity capabilities.
Solution Approach 2:
The patent introduces an intermediary direct data transfer mechanism between communication modules that bypasses the CPU. This intermediary path allows data to be exchanged between different buses through the communication modules themselves, maintaining adaptability and versatility while significantly reducing the processing burden on the CPU.
3Productivity
If data is transferred through buffering in memory, then data can be stored and processed, but transfer time increases and bus utilization decreases
Solution Approach 1:
The patent extracts the buffering step from the data transfer process by implementing direct data transfer between communication modules. Data is transferred directly from the source bus to the destination bus without being buffered in memory, thereby eliminating the time penalty associated with buffering operations and maximizing bus utilization efficiency.
Data Source
AI summary
A gateway for data transfer between serial buses, including multiple communication modules that are each provided for connection of one serial bus, and that carry out a conversion between data packets and data words, a bus master that, via an internal control bus, controls a word-based transfer of data via an internal data bus between two communication modules, the bus master applying a source address via a source address bus to an internally transmitting first communication module, and a destination address via a separate destination address bus to an internally receiving second communication module, data received in data packets by the first communication module via a first serial bus connected thereto being transferred from the first communication module directly without buffering, in word-based fashion in one or more data words, via the internal data bus to the second communication module, which delivers these transferred data, in data packets, via a second serial bus connected to the second communication module.