Serial Bus Glitch Filtering With AFSM Edge Rejection
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Solution Overview
Problem
Existing serial interface buses in integrated circuits face issues with signal integrity due to glitches and noise, particularly at higher clock frequencies, leading to read/write failures and system failures.
Innovation Solution
Implementing a glitch filter with an asynchronous finite state machine (AFSM) and a glitch detector, along with automatic slew rate control and programmable output impedance, to reject glitches and improve signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher clock frequencies are used in serial interface buses, then data transmission speed is improved, but signal integrity deteriorates due to glitches and noise
Solution Approach 1:
A glitch filter circuit is introduced as an intermediary component between the serial interface bus and the receiving device. This filter acts as a mediator that allows legitimate high-speed signals to pass through while blocking glitch signals, thus enabling high data transmission speed without compromising signal integrity. The filter circuit includes detection logic that identifies glitch characteristics and blocks them before they can cause read/write failures.
Solution Approach 2:
The harmful glitch signals are extracted and separated from the legitimate data signals using the glitch filter. The filter detects the distinctive characteristics of glitch signals (such as abnormal pulse widths or voltage levels) and extracts them from the signal stream, allowing only clean data signals to be transmitted to the receiving device. This extraction process maintains high transmission speed while eliminating noise interference.
2Reliability
If glitch filtering is implemented to improve signal integrity, then read/write failures are reduced, but device complexity increases
Solution Approach 1:
The glitch filter functionality is merged with the existing serial interface buffer circuitry rather than being implemented as a completely separate component. The detection logic and filtering mechanisms are integrated into the buffer's existing structure, sharing common resources such as signal paths and control logic. This merging approach provides effective glitch filtering while minimizing the increase in overall device complexity.
Solution Approach 2:
The glitch filter circuit is designed to perform multiple functions: it filters glitch signals, maintains signal integrity, and can operate across different voltage domains. The same circuit structure handles both normal data transmission and glitch rejection, making it a multi-functional component that reduces the need for additional dedicated circuits. This universal design approach improves reliability without proportionally increasing complexity.
Data Source
AI summary
Various aspects of the present disclosure generally relate to integrated circuits. In some aspects, a glitch filter associated with a serial interface bus may receive an input signal associated with a glitch. The glitch filter may reject the glitch based at least in part on a plurality of state machine transitions associated with the glitch filter and a set of timers associated with the glitch filter, to produce an output signal that is not associated with the glitch. The glitch filter may provide the output signal. Numerous other aspects are described.