Serial Bus Protocol Low Latency Interrupts SoC
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Solution Overview
Problem
Conventional data processor bus systems, especially in System on a Chip (SoC) architectures, face challenges with high latency and inefficiencies in handling multiple data streams due to skew errors and the need for clocking signals, which limits their ability to provide fast and flexible control and interrupt signals.
Innovation Solution
A protocol that utilizes a datalink layer coupled with a physical layer to multiplex abstract protocols, allowing for low-latency flow control and signaling by separating data and control signals and using an abstract protocol that interacts only with the lowest protocol layers, enabling efficient communication over point-to-point bus architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional parallel buses are used for data transfer, then data transfer capability is improved, but skew errors occur and device complexity increases
Solution Approach 1:
The patent replaces conventional parallel mechanical bus structures with a serial communication protocol that uses multilevel signaling (PAM-5) to achieve high-speed data transfer without the skew errors inherent in parallel buses. The serial interface with embedded clocking eliminates the need for multiple synchronized signal paths.
2Productivity
If conventional serial buses with clocking are used, then data transfer is achieved, but device complexity increases due to clocking requirements
Solution Approach 1:
The patent merges the data signal and clock signal into a single communication channel by embedding clock information within the data stream using multilevel signaling. The PAM-5 encoding scheme allows clock recovery without requiring separate clock lines, thereby reducing device complexity while maintaining high-speed serial communication capabilities.
3Reliability
If higher layer protocols are used for flow control, then communication reliability is improved, but response time increases due to additional headers
Solution Approach 1:
The patent extracts flow control functionality from higher protocol layers and implements it directly at the physical layer through dedicated control channels. This allows flow control signals to be transmitted immediately without waiting for data frame boundaries or processing through multiple protocol layers, significantly reducing response time while maintaining reliable flow control.
4Loss of time
If short frames are used for low latency signaling, then response time is improved, but bandwidth utilization decreases due to framing overhead
Solution Approach 1:
The patent creates a universal signaling mechanism that can operate within data frames of any length by embedding control signals in the reverse channel. The same physical interface and protocol structure handle both data transmission and control signaling, eliminating the need for separate short frames and maximizing bandwidth utilization while maintaining low latency for control operations.
Data Source
AI summary
Disclosed are methods and apparatus to control data and command flow over a physical communications channel between a transmitter and a receiver, and more specifically to provide a protocol for a point-to-point serial bus architecture with low latency time for flow control and other signaling, regardless of the length of the data packet frame. The abstract data flow control protocol can be employed by various buses as it interacts only with the lowest protocol layers. Separate buffers for data and control can be used to allow the bus to be compatible with slower buses also to support additional control functions without involving a higher protocol layer.