Serial Bus Repeater Power State Detection Circuit
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Solution Overview
Problem
Existing serial bus repeaters require expensive digital circuitry like PLL and CDR to detect the transition from L0 to L1 power state, increasing their size and cost.
Innovation Solution
A serial bus repeater circuit that identifies the L0 to L1 power state transition by detecting power state transactions and measuring the impedance of the serial bus termination resistance without using PLL or CDR circuitry, utilizing a power state transaction identification circuit and a bus state identification circuit with a switch, current source, and comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PLL and CDR circuitry are used to detect power state transitions, then detection accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts and removes the complex PLL and CDR circuitry from the repeater design, retaining only the essential functionality needed for power state detection. By taking out these expensive digital components and using simpler analog circuitry instead, the patent achieves the same detection capability with reduced complexity and cost.
Solution Approach 2:
The patent replaces expensive, complex digital circuitry (PLL and CDR) with cheaper, simpler analog components. The invention uses basic electronic components that are less costly and simpler to implement while achieving the required detection function, effectively substituting expensive objects with cheaper alternatives.
2Reliability
If PLL and CDR circuitry are used to detect power state transitions, then detection reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive digital components (PLL and CDR circuits) with cheaper analog components that are easier and less costly to manufacture. This substitution maintains detection reliability while significantly reducing the manufacturing cost and complexity of the repeater device.
Solution Approach 2:
The patent substitutes complex digital electronic systems (PLL and CDR circuitry) with simpler analog electronic circuits. This replacement eliminates the need for sophisticated digital signal processing while achieving reliable power state detection through simpler, more manufacturable analog components.
3Measurement precision
If packet decoding is performed to identify power state transactions, then detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the packet decoding functionality from the repeater, recognizing that full decoding is unnecessary for power state detection. By taking out this complex digital processing capability and using simpler signal analysis, the patent reduces device complexity while maintaining the ability to accurately identify power state transactions.
Solution Approach 2:
The patent uses a simplified approach that copies only the essential features needed for power state detection rather than implementing full packet decoding. By copying only the necessary signal characteristics and patterns, the patent achieves accurate detection without the complexity of complete protocol interpretation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the detection of L0 to L1 power state transitions without decoding packets, reducing the size and cost of the repeater while maintaining accurate power state identification.
Implementation Method 1
The comparator includes a first input coupled to the first terminal of the switch, and a second input coupled to a threshold voltage source
Data Source
AI summary
A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.