Serial-Bus Timed-Trigger Synchronization via Counter Hold States

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Solution Overview

Problem

Existing serial communication systems face challenges in accurately and reliably synchronizing time-critical triggers over shared serial buses, particularly in mobile communication devices, due to complexities arising from timer-based trigger actuation and varying counter load offsets, which increase hardware complexity and latency.

Innovation Solution

The proposed solution involves disabling counters or timers until they are loaded with count values, and using Bus Park Condition (BPC) detection to synchronize trigger actuation by enabling counters simultaneously, thereby reducing computational burden and hardware complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If counters are enabled immediately upon receiving count values, then trigger actuation responsiveness is improved, but trigger synchronization accuracy deteriorates due to varying counter load offsets

Engineering Contradiction:
Improvetrigger actuation responsivenessVSAvoidtrigger synchronization accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by disabling counters until all count values are received and loaded. This ensures that all counters start counting at the same moment (when enabled simultaneously after loading), eliminating synchronization errors caused by staggered loading. The counters are prepared in advance with their respective values but held in a disabled state until the precise moment when simultaneous activation is required.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If counters are disabled until all are loaded with count values, then trigger synchronization accuracy is improved, but trigger actuation latency increases

Engineering Contradiction:
Improvetrigger synchronization accuracyVSAvoidtrigger actuation latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent resolves this contradiction by performing preliminary loading of all counter values before enabling the counters. By receiving and loading all count values in advance while keeping counters disabled, the system eliminates synchronization errors without incurring runtime delays. The enabling action occurs immediately after all values are loaded, minimizing the disabled period.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses the incoming datagram structure to automatically load counter values in sequence as they are received over the serial bus. The counters service themselves by being configured with their values during the normal data reception process, eliminating the need for separate configuration operations and reducing overall latency.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If multiple counters are configured with different load offsets, then individual trigger timing flexibility is improved, but hardware complexity increases due to synchronization management

Engineering Contradiction:
Improveindividual trigger timing flexibilityVSAvoidsynchronization management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the synchronization control for multiple counters into a single unified mechanism. Instead of managing each counter's enable/disable state independently, the system uses a common enable signal that is activated simultaneously for all counters after their values are loaded. This unified approach maintains individual timing flexibility through different count values while eliminating complex per-counter synchronization management.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4278271B1Timed-trigger synchronization enhancement
Publication Date: 2025.07.09 QUALCOMM INC
  • EP4278271B1 patent drawingFigure 1
  • EP4278271B1 patent drawingFigure 2
  • EP4278271B1 patent drawingFigure 3

AI summary

Systems, methods, and apparatus improve synchronization of trigger timing when triggers are configured over a serial bus. A data communication apparatus has an interface circuit that couples the data communication apparatus to a serial bus and is configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the counters to refrain from counting until all of the counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.