Serial Bus Interface Using Bus-Derived Vdd Reference
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Solution Overview
Problem
Providing an interface to a serial communications bus that avoids the need for a direct electrical connection to the voltage Vdd, which is costly due to requiring additional area and pins on semiconductor devices, especially when electronic devices are powered by voltages greater than or equal to Vdd.
Innovation Solution
Employing a peak detector to generate a DC voltage reference that approximates Vdd, using transistors with gates coupled to the SCL and SDA lines, and utilizing Schmidt triggers and level shifters powered by a higher voltage Vcc to decode signals without a direct connection to Vdd.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a direct electrical connection from voltage Vdd to the integrated circuit is provided, then the input circuitry can properly interpret logic levels on the serial communications bus, but additional area on the semiconductor device and additional pins in the semiconductor package are required
Solution Approach 1:
The patent introduces an intermediary voltage reference generation circuit that couples to the serial communications bus lines (SDA and SCL) through existing pins without requiring a direct Vdd connection. This circuit generates an internal voltage reference that mediates between the bus voltage levels and the internal logic level interpretation, allowing accurate signal interpretation while avoiding the need for additional Vdd connection pins and reducing semiconductor device area.
2Reliability
If a direct electrical connection from voltage Vdd to the integrated circuit is provided, then the input circuitry can properly interpret logic levels on the serial communications bus, but another pin in the semiconductor package is required which may increase package size
Solution Approach 1:
The patent makes the existing serial communication pins (SDA and SCL) serve multiple functions: they not only transmit data and clock signals but also provide voltage reference information for internal logic level interpretation. By coupling the voltage reference generation circuit to these existing pins, the design achieves proper signal interpretation without adding dedicated Vdd connection pins, thereby reducing package complexity and pin count.
3Adaptability or versatility
If electronic devices are powered by voltages greater than or equal to Vdd, then higher voltage circuitry can be used, but a direct connection to Vdd is needed for proper signal interpretation
Solution Approach 1:
The patent changes the voltage reference parameter by generating an internal voltage reference through a circuit that couples to the serial communications bus lines. This internal reference adapts to the bus voltage levels regardless of whether the electronic device is powered by voltages greater than or equal to Vdd. The voltage reference generation circuit transforms the external bus voltage information into an internal reference parameter that enables proper logic level interpretation across different voltage conditions, eliminating the need for direct Vdd connection requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables proper decoding of data and clock signals on the serial communications bus without a direct electrical connection to Vdd, reducing the need for additional pins and package size, while maintaining compatibility with higher voltage circuitry.
Implementation Method 1
the electronic devices employ a peak detector to generate a DC voltage reference that approximates the voltage Vdd
Implementation Method 2
The peak detector includes transistors having gates electrically coupled to the SCL and SDA communications lines. The sources of the transistors are coupled to a capacitor in a source follower configuration
Implementation Method 3
The sources of the transistors are coupled to a capacitor in a source follower configuration. When the gates of the transistors are pulled high by the respective pull-up resistors, the sources of the respective transistors charge the capacitor to a voltage Vcap
Implementation Method 4
Schmidt triggers receive and recover the logic signals on the SCL and SDA serial communications lines and the DC reference voltage Vcap is used as the voltage source for the Schmidt triggers
Implementation Method 5
Each Schmidt trigger has an output that is coupled to the input of a level shifter. The level shifters are powered by a voltage Vcc which is typically greater than or equal to the voltage Vdd
Data Source
AI summary
An interface within an electronic device coupled to a serial communications bus having one or more serial communications lines generates a reference voltage source within the electronic device from the logic signals carried on the serial communications line(s). The generated reference voltage source is used within the electronic device to decode the logic signals received from the serial communications line(s).