Serial Content Addressable Memory Pipelined DRAM SRAM
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Solution Overview
Problem
Traditional content addressable memories (CAMs) face limitations in density and latency due to their serial data access methods, which hinder their ability to efficiently handle high-speed serial digital streams in communications, especially in routers and switches, where the latency increases with the number of chips required to store data.
Innovation Solution
A pipelined approach is implemented to serially access data within a high-density DRAM or SRAM memory, organizing the memory core with more bit lines than word lines, allowing each word line to address one bit across all words, enabling simultaneous comparison of input data with memory data and reducing latency by allowing pre-fetch and look-ahead logic to eliminate delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional CAM structures are used to achieve content addressable memory function, then the memory can perform content comparison, but the density is limited and the size is restricted to under a megabit per chip
Solution Approach 1:
The patent uses DRAM or SRAM memory cells (which require 1-6 transistors per bit) to store CAM data, rather than using dedicated CAM structures (which require 8-16 transistors per bit). This copying approach allows the system to achieve CAM functionality with lower-density memory structures, thereby increasing overall memory density while reducing the transistor count per stored bit.
Solution Approach 2:
The patent introduces a time dimension to the comparison process by serially shifting input data bits through the memory array over multiple clock cycles. Instead of performing parallel comparison across all bits simultaneously (spatial dimension), the system performs sequential comparison over time, allowing dense memory structures to be used without requiring complex parallel comparison logic for each bit.
2Loss of time
If serial data access method is used in traditional CAM, then the structure is simpler, but the latency increases especially when multiple chips are required to store data
Solution Approach 1:
The patent implements a pipelined architecture where input data bits are shifted into the memory array in advance during clock cycles N through 1. By the time the most significant bit is compared, all less significant bits have already been loaded and are ready for comparison in subsequent cycles. This preliminary action allows overlapping of data loading and comparison operations, reducing the total access latency.
Solution Approach 2:
The patent maintains continuous operation by pipelineing the comparison process across multiple clock cycles. While one set of data is being compared, the next set of data is being loaded into the memory array. This continuous pipeline operation ensures that the memory system is always productive, eliminating idle time between comparison operations and reducing average access latency.
3Quantity of substance
If DRAM structures are used to increase memory density, then the cost efficiency improves, but the access speed becomes quite slow
Solution Approach 1:
The patent uses dynamic serial shifting of data bits through the memory array, where data is continuously shifted in and out over multiple clock cycles. This dynamic approach allows DRAM's inherent speed limitations to be overcome by distributing the comparison operation across multiple cycles, with each cycle operating at DRAM's comfortable speed while the overall system achieves high throughput through pipelining.
4Speed
If SRAM structures are used to improve access speed, then the latency reduces, but the transistor requirement increases to 3-6 transistors per bit
Solution Approach 1:
The patent makes the memory system universally applicable by showing that the same serial pipelined architecture works with both DRAM (1 transistor per bit) and SRAM (3-6 transistors per bit) structures. The system achieves CAM functionality regardless of the underlying memory technology, allowing designers to choose between DRAM for maximum density or SRAM for maximum speed based on their specific application requirements.
Data Source
AI summary
A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also presented.