High Density Serial Capacitor Logic Integration
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Solution Overview
Problem
The manufacturing of complex semiconductor devices is inefficient and costly due to separate design rules and process flows for memory and logic regions, and the integration of high-density capacitors is challenging, especially with copper-based capacitors, which are difficult to etch and require time-consuming damascene processes.
Innovation Solution
A high-density serial capacitor device is developed with a structure comprising a bottom electrode, a middle electrode, and a top electrode, where the electrodes are conductively coupled, and dielectric layers are used between them, allowing for a more integrated and efficient manufacturing process that eliminates the need for complex etching of metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate design rules and process flows are used for memory and logic regions, then each region can be optimized independently, but manufacturing efficiency decreases and costs increase
Solution Approach 1:
The patent merges the design rules and process flows for memory and logic regions into a unified approach. By making the capacitor structure in the logic region compatible with memory cell capacitor structures and using the same fabrication processes, the patent eliminates the need for separate processing, thereby improving manufacturing efficiency while maintaining region-specific optimization through shared process parameters
2Manufacturing precision
If traditional etching processes are used for copper-based capacitors, then metal layer patterning can be achieved, but the process becomes time-consuming and complex
Solution Approach 1:
The patent extracts the etching step from the capacitor fabrication process by using a damascene approach where copper is deposited conformally and then planarized. This removes the complex etching process entirely, reducing fabrication time and complexity while maintaining precise metal layer patterning through the self-aligned nature of the deposition and planarization steps
3Device complexity
If damascene process is used for copper-based capacitors, then etching complexity is reduced, but the process becomes even more time-consuming
Solution Approach 1:
The patent segments the capacitor formation process into distinct modular steps that can be performed using standard fabrication equipment. By dividing the process into separate deposition, planarization, and patterning stages that align with existing logic circuit fabrication sequences, the patent reduces overall process time while maintaining simplicity
4Area of stationary object
If capacitor area is reduced to increase integration density, then more capacitors can be fitted on chip, but capacitance value may become insufficient
Solution Approach 1:
The patent uses composite dielectric structures with multiple layers having different dielectric constants. By stacking dielectric layers with varying k-values between the capacitor plates, the patent achieves high capacitance values in a reduced area, thereby increasing integration density while maintaining sufficient capacitance for memory operations
Data Source
AI summary
A serial capacitor comprised of a bottom electrode, a top electrode that is conductively coupled the bottom electrode, a middle electrode positioned between the bottom and top electrode, a lower dielectric layer positioned between the bottom and middle electrodes, and an upper dielectric layer positioned between the middle and the electrodes. A method includes forming the bottom electrode in a first layer of insulating material, forming the lower dielectric layer and the middle electrode above the bottom electrode, wherein the middle electrode is positioned in a second layer of insulating material, forming the upper dielectric layer above the middle electrode, forming an opening that exposes a portion of the bottom electrode, and forming the top electrode above the upper dielectric layer, wherein a portion of the top electrode extends through the opening and contacts the bottom electrode.