Serial Communication Circuit With Timer Reset for Clock Pulse Errors
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Solution Overview
Problem
Existing serial communication circuits face errors due to delays in the output timing of the serial clock signal, which can lead to disrupted communication, especially when pulses are missed or duplicated, causing errors in data transmission and requiring manual reset to restore normal communication.
Innovation Solution
A serial communication circuit with a data counter that increments with each pulse of the serial clock signal and a timer circuit that outputs a timer signal after a predetermined interval, clearing the data counter and resetting the communication state, ensuring normal operation even with missed or extra pulses and timing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the timer circuit starts counting from the first clock pulse, then the counting timing is synchronized with the clock signal, but when the clock signal timing is delayed due to interrupts, the timer and data counter become desynchronized causing communication errors
Solution Approach 1:
The data counter is cleared to zero in advance by the timer circuit before data transmission begins. This preliminary clearing ensures that even if the clock signal timing is delayed due to interrupts, the data counter will start counting from the correct position, preventing desynchronization between the timer circuit and data counter, and thus maintaining communication reliability without requiring complex synchronization mechanisms
2Reliability
If the timer circuit clears the data counter at fixed intervals, then communication synchronization is maintained, but the system cannot handle delayed clock signal output timing
Solution Approach 1:
The timer circuit generates a timer signal that feeds back to clear the data counter to zero. This feedback mechanism ensures that the data counter is continuously reset to the correct starting position based on the timer circuit's counting, allowing the system to maintain accurate data transmission synchronization while adapting to delayed clock signal output timing caused by interrupts or other delays
Data Source
AI summary
A serial communication circuit for performing full duplex serial communication with a microcomputer includes a counter and a timer. The counter is incremented by each pulse of a serial clock signal output from the microcomputer. When the counter reaches the number of bits of serial data output from the microcomputer, the counter outputs a load signal to a receiving register. The timer starts to count after the counter outputs the receiving load signal for the first time and continues to count during the serial communication. The timer expires at a predetermined time interval. Each time the timer expires, the timer outputs a timer signal. In response to the timer signal, a synchronous signal is output to the microcomputer, the counter is cleared to zero, and data to be output to the microcomputer is loaded into a sending register.