Serial Clock Edge Timing for High-Speed Data Links
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Solution Overview
Problem
Traditional serial data communications systems are limited by propagation delays, which restrict their operating speed and can result in inaccurate data transmission.
Innovation Solution
The system alternates between shifting out and shifting in data bits relative to different edges of a shift clock signal, with a first time difference followed by a second time difference that is longer than the first, to accommodate propagation delays and enable faster data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional serial data communications are used, then the system is simple to implement, but the operating speed is limited by propagation delay
Solution Approach 1:
The patent applies preliminary action by having the transmitter shift out the SDO bit before the receiver is ready to shift in the SDI bit. Specifically, the transmitter triggers the SDO bit shifting out at a time that is earlier than the receiver can reliably shift in the corresponding SDI bit, allowing the data to be prepared in advance and ensuring accurate transmission despite propagation delays
2Productivity
If faster data transmission is implemented, then productivity increases, but propagation delay causes inaccurate data transmission
Solution Approach 1:
The system implements preliminary action by having the transmitter initiate the SDO bit shifting out process before the receiver completes its SDI bit shifting in process. This time advancement allows the data to be prepared and sent ahead, ensuring that even at higher transmission rates, the receiver has sufficient time to accurately capture the incoming data despite propagation delays
3Reliability
If the shift clock edges are used simultaneously for shifting in and out, then the system complexity is low, but the data stability during transmission is compromised
Solution Approach 1:
The patent applies preliminary action by having the transmitter trigger the SDO bit shifting out at a time earlier than the receiver triggers the SDI bit shifting in. This creates a time offset where the data is prepared and sent in advance, ensuring data stability during transmission. The timing control involves using a shift clock signal with controlled edges where the transmitter's SDO shifting out is triggered before the receiver's SDI shifting in
4Speed
If propagation delay is not compensated, then the system is simple to operate, but the operating frequency is limited
Solution Approach 1:
The system compensates for propagation delay by having the transmitter initiate the SDO bit shifting out process before the receiver is ready to shift in the SDI bit. This time advancement effectively compensates for the propagation delay, allowing the system to operate at higher frequencies. The timing configuration uses a shift clock signal where the transmitter's triggering of SDO shifting out occurs at an earlier time than the receiver's triggering of SDI shifting in
Data Source
AI summary
A serial communications device alternates between triggering the shifting out of an SDO bit and triggering the shifting in of an SDI bit relative a first shift clock edge and a second shift clock edge of a shift clock signal SCLK that are separated by a first time difference. The serial communication device is further configured to trigger the shifting in of the SDI bit separated from triggering the shifting out of the SDO bit by a second time difference that is longer than the first time difference.