Serial Clock Generation Using Half-Speed Orthogonal Clocks
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Solution Overview
Problem
High speed serial transmitters face limitations due to the performance bottlenecks in serializer and driver component implementations, particularly in generating full speed clock signals, and require efficient solutions that combine multiplexing functionality in a single stage while operating at lower power.
Innovation Solution
A transmission system incorporating an oscillator with a compensator and a serializer that generates orthogonal clock signals at half frequency, which are then combined by a driver using XOR logic to produce a full clock frequency output data stream, improving accuracy, noise performance, and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a full speed clock signal is generated in the serializer to achieve high speed transmission, then the transmission speed increases, but the performance bottleneck and power consumption increase
Solution Approach 1:
The patent segments the clock signal generation into two separate half-speed clock signals instead of generating one full-speed clock signal. The serializer divides the full-speed data stream into two half-speed streams, each processed by separate serializer cores with their own half-speed clock signals. This segmentation reduces the frequency requirements for clock generation and distribution, thereby reducing power consumption while maintaining the overall high-speed transmission capability through parallel processing.
2Speed
If the oscillator frequency is increased to achieve higher transmission speeds, then the transmission speed improves, but the noise performance deteriorates
Solution Approach 1:
The patent segments the single high-frequency oscillator into two separate lower-frequency oscillators, each generating half-speed clock signals. This segmentation allows each oscillator to operate at a lower frequency with reduced jitter and noise characteristics. The parallel processing architecture ensures that the lower-frequency oscillators can maintain stable operation without the noise and jitter issues that plague high-frequency single-oscillator designs, thereby improving overall noise performance while achieving high-speed transmission.
3Productivity
If a serializer with multiplexer implementation is used to combine half speed bit streams, then the full speed bit rate is achieved, but the device complexity and power consumption increase
Solution Approach 1:
The patent merges the multiplexer functionality directly into the serializer core logic, eliminating the need for a separate multiplexer stage. The serializer cores incorporate built-in multiplexing capability that allows them to efficiently combine half-speed bit streams into full-speed output without requiring external multiplexer components. This integration reduces device complexity by consolidating functions and simplifies the overall architecture while maintaining high bit rate performance.
Data Source
AI summary
A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.