Serial Transmitter Clock Generation Using Half-Rate I/Q Streams
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Solution Overview
Problem
High speed serial transmitters face limitations due to the performance bottlenecks in serializer and driver component implementations, particularly in generating full speed clock signals, and there is a need for an efficient high speed current mode driver that combines multiplexing functionality in a single stage while operating at lower power.
Innovation Solution
The proposed solution involves a transmission system with an oscillator generating orthogonal clock signals, a serializer modulating data streams based on these clock signals, and a driver combining the streams using XOR logic to achieve a full clock frequency output, with a compensator ensuring phase alignment to reduce noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a serializer generates a full speed clock signal to achieve high data transmission speed, then the transmission speed increases, but the circuit complexity and design difficulty increase, creating a performance bottleneck
Solution Approach 1:
The patent divides the high-speed data transmission task into multiple parallel lower-speed channels. Instead of using a single full-speed clock signal, the system uses multiple half-speed clock signals to process data in parallel streams, which are then combined to achieve the equivalent of full-speed transmission. This segmentation reduces the complexity of clock generation and circuit implementation while maintaining high data throughput.
Solution Approach 2:
The patent combines multiple parallel data streams from different channels into a single high-speed output stream. By merging the outputs of multiple half-speed channels that are properly phased and synchronized, the system achieves full-speed transmission capability without requiring a single complex full-speed clock generator, thus resolving the technical contradiction.
2Speed
If separate serializer and driver components are used to achieve high speed transmission, then the transmission speed requirement is met, but the system complexity and power consumption increase
Solution Approach 1:
The patent integrates the serializer and driver functions into a single unified stage. The driver component is designed to simultaneously perform multiplexing of multiple data streams and driving the output, eliminating the need for a separate serializer stage. This merging reduces system complexity and component count while maintaining high-speed transmission capability.
Solution Approach 2:
The driver component is designed with multi-functionality, serving both as a buffer/driver and as a multiplexer. By making the driver universal and capable of handling multiple functions, the system eliminates redundant components and simplifies the overall architecture while achieving the required transmission speed.
3Productivity
If traditional driver implementations are used to combine data streams, then the function is achieved, but power consumption increases
Solution Approach 1:
The patent replaces traditional voltage-mode driver implementations with current-mode logic (CML) for the driver stage. Current-mode operation allows for more efficient switching and signal combining of multiple data streams, reducing power consumption compared to conventional voltage-mode approaches while maintaining the capability to combine multiple streams effectively.
Data Source
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AI summary
A transmission system may include an oscillator (110), a serializer (120), and a driver (130). The oscillator (110) may generate at least two clock signals (I,Q). The serializer (120) may modulate a plurality of data streams (S1,S2) based upon the at least two clock signals (I,Q) and a plurality of channels of data (D1,D2). The driver (130) may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.