Synchronous Serial Clock Timing for Long Differential Cables
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Solution Overview
Problem
In automation technology, the maximum cable length for reliable synchronous serial data transmission is limited by the ability of differential receivers to restore digital signals, leading to signal deformation due to charge transfer processes over long lines, restricting the effective range of position-measuring devices and other applications.
Innovation Solution
A device with a clock generator configured to extend the duration of the first clock phase of the clock pulse train during data transmission cycles, ensuring the differential voltage reaches maximum levels without exceeding the receiver's capacity, thereby maintaining signal integrity over longer lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If data transmission takes place over long cable lengths using differential signals, then the effective range of position-measuring devices is extended, but signal deformation occurs due to charge transfer processes limiting reliable transmission
Solution Approach 1:
The patent changes the temporal parameters of the clock signal by extending the duration of the first clock phase in dynamic operating states. This parameter modification allows the differential voltage to reach maximum levels without exceeding receiver capacity, compensating for signal degradation over long cable lengths and maintaining reliable transmission.
2Reliability
If the maximum occurring differential voltage is kept below the maximum differential voltage of the clock transmitter block in dynamic operating states, then signal integrity is maintained, but the clock phase duration must be extended reducing transmission efficiency
Solution Approach 1:
The patent implements dynamic clock phase duration adjustment based on operating state. In dynamic operating states where maximum occurring differential voltage is below the transmitter block's maximum, the first clock phase duration is extended. This dynamic adaptation ensures reliable signal interpretation while optimizing transmission efficiency for different operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the maximum achievable line length for synchronous serial interfaces by ensuring correct signal interpretation and transmission, even in dynamic operating states, without requiring adaptations to the data controller or interface protocol.
Implementation Method 1
The transmit clock signal is fed to the clock transmitter block, which converts the transmit clock signal into a differential clock signal for output via the differential clock channel
Implementation Method 2
a differential data signal arriving via the differential data channel is fed to the data receiver block, which converts the differential data signal into a data signal
Implementation Method 3
The line pairs used for transmission have, in addition to ohmic resistance, both capacitive and inductive properties, which are dependent on the length of the line
Implementation Method 4
The line pairs used for transmission have, in addition to ohmic resistance, both capacitive and inductive properties
Implementation Method 5
The resulting charge transfer processes during data transmission lead to deformation of the transmitted signals
Data Source
AI summary
A device for synchronous serial data transmission over a differential data channel and a differential clock channel includes an interface controller having a clock generator, data controller, clock transmitter block and data receiver block. The clock generator generates a transmit clock signal which, during a data transmission cycle, includes a clock pulse train having a period. The clock generator is suitably configured such that, for data transmission cycles in a dynamic operating state in which a maximum occurring differential voltage of a differential clock signal is lower than a maximum differential voltage of the clock transmitter block, the clock generator sets a duration of a first clock phase of a first clock period of the clock pulse train to be longer than a first clock phase of following clock periods and shorter than a time duration required to reach the maximum differential voltage.