Serial Data Receiving Circuit With Embedded Clock Recovery
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Solution Overview
Problem
High-speed serial data transmission over a single transmission line is challenging due to propagation delays and synchronization issues between clock and data signals, especially when using low voltage differential signaling (LVDS), where conventional methods require additional lines for sequence control and oscillators, limiting transmission rates.
Innovation Solution
A receiving circuit with a voltage-controlled oscillator, frequency dividers, a phase/frequency comparator, and a control voltage generator allows for high-speed serial data transmission over a single line by recovering the sampling clock signal from embedded clock data, using level shifts and synchronization codes to reduce frequency bias and enhance clock signal recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LVDS transmission is used with separate clock and data signal lines, then synchronization can be maintained, but transmission speed is limited to below 1 Gbps due to propagation delay differences
Solution Approach 1:
The patent combines the clock signal and data signal into a single transmission line by embedding the clock information within the data stream. The transmitting circuit generates serial data that includes both data and embedded clock information, which is then transmitted over one differential transmission line instead of requiring separate lines for clock and data signals.
Solution Approach 2:
The receiving circuit extracts the clock signal from the embedded clock information within the serial data stream. By monitoring changing points in the received serial data, the CDR circuit recovers the clock signal and uses it to latch the data at appropriate timing, eliminating the need for separate clock line transmission.
2Reliability
If a return transmission line is added for sequence adjustment signals, then synchronization can be maintained during reset operations, but the system complexity increases
Solution Approach 1:
The patent eliminates the need for a separate return transmission line by integrating the sequence adjustment function into the main data transmission line. The same differential transmission line that carries serial data also handles sequence adjustment signals, removing the requirement for additional dedicated signal paths.
3Reliability
If oscillators are added to both transmitting and receiving circuits, then clock synchronization can be achieved, but the system requires more components and cannot dynamically change transmission rate
Solution Approach 1:
The receiving circuit generates its own clock signal by recovering it from the embedded clock information in the received serial data. The CDR circuit autonomously extracts the clock signal and adjusts its timing to synchronize with the transmitted data, eliminating the need for a separate oscillator at the receiving end while maintaining synchronization.
Solution Approach 2:
The system enables dynamic transmission rate changes by allowing the receiving circuit to adaptively recover the clock signal at different frequencies. Since the clock is extracted from the data stream rather than generated by a fixed-frequency oscillator, the transmission rate can be dynamically adjusted without hardware changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable high-speed serial data transmission without sequence control or oscillators, suppressing jitter and improving clock signal trackability, thus overcoming synchronization challenges and increasing transmission efficiency.
Implementation Method 1
a voltage controlled oscillator that generates a sampling clock signal having a frequency based on an input control voltage
Implementation Method 2
a first frequency divider that divides the frequency of the sampling clock signal at a division rate M; a second frequency divider that divides a frequency of a clock signal based on the received serial data at a division rate N
Implementation Method 3
a phase/frequency comparator that generates a phase/frequency difference signal based on a phase difference between an output signal of the first frequency divider and an output signal of the second frequency divider
Implementation Method 4
a control voltage generating circuit that generates the control voltage to control a frequency of the voltage controlled oscillator based on the phase/frequency difference signal
Data Source
AI summary
A receiving circuit which receives serial data, includes: a voltage controlled oscillator which generates a sampling clock signal having a frequency based on an input control voltage; a first frequency divider which divides the frequency of the sampling clock signal at a division rate M; a second frequency divider which divides a frequency of a clock signal based on the received serial data at a division rate N, N being a real number represented by M×q/p; a frequency comparator which generates a phase/frequency difference signal based on a phase difference between an output signal of the first frequency divider and an output signal of the second frequency divider; and a control voltage generating circuit which generates the control voltage to control a frequency of the voltage controlled oscillator based on the phase/frequency difference signal.