Serial Data Clock Acquisition by Transition Counting
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Solution Overview
Problem
Conventional receivers for synchronous serial data streams are limited to operating at a single pre-programmed clock frequency, restricting their ability to handle data streams with varying frequencies, and require auxiliary acquisition systems due to the limited frequency discrimination capability of XOR-based phase detectors in clock recovery PLLs.
Innovation Solution
A method that automatically determines the clock frequency of a serial data stream by coarsely selecting a high reference clock, counting data transitions at multiple sample frequencies, and refining the frequency using sub-reference clocks to achieve a stable data clock, compliant with SONET and SDH standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional receiver uses a pre-programmed operating frequency, then the device complexity is reduced, but the adaptability to different communication protocols is limited
Solution Approach 1:
The system performs preliminary coarse frequency determination by counting data transitions at multiple sample frequencies before the PLL acquisition stage. This preliminary action establishes an initial frequency estimate that guides the subsequent fine acquisition process, enabling the receiver to adapt to different clock rates without requiring complex pre-programming
Solution Approach 2:
The invention replaces the mechanical approach of pre-programming fixed frequencies with an automated electronic frequency determination system. The system uses digital counting of data transitions at multiple sample frequencies to automatically identify the operating clock rate, substituting electronic adaptation for mechanical configuration
2Measurement precision
If a PLL uses an XOR-based phase detector, then the circuit is simpler to implement, but the frequency discrimination capability is limited
Solution Approach 1:
The frequency determination process is segmented into two distinct stages: a coarse frequency determination stage that counts data transitions at multiple sample frequencies to establish an initial frequency estimate, and a fine acquisition stage using the PLL with XOR phase detector. This segmentation allows the simple XOR detector to operate within its capabilities while the coarse stage provides the necessary frequency discrimination
Solution Approach 2:
The coarse frequency determination system acts as an intermediary between the incoming data stream and the PLL phase detector. It processes the signal first to establish frequency boundaries, then passes control to the PLL for fine-tuning, enabling the simple XOR detector to achieve accurate frequency lock without requiring complex frequency discrimination capabilities
3Adaptability or versatility
If the VCO tuning range is made wider to cover multiple frequencies, then the adaptability increases, but the PLL stability deteriorates
Solution Approach 1:
The coarse frequency determination performs preliminary action by identifying the approximate frequency range before the PLL engagement. This allows the system to configure the PLL parameters appropriately for the detected frequency range, maintaining stability while covering multiple frequencies through adaptive parameter selection rather than relying solely on wide VCO tuning range
Data Source
AI summary
A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer ≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x−1).