Serial Communication Device for Memory Access
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Solution Overview
Problem
The increasing use of hardware acceleration devices for processing large amounts of data leads to high network loads due to the need for direct memory access between these devices and external memory, which can overwhelm network resources.
Innovation Solution
A serial communication system and device that utilize a system-on-chip (SoC) bus interface, a master protocol processor, and a serial transceiver to convert request transactions into packets according to a predetermined protocol, allowing for efficient transmission and reception of data between hardware acceleration devices and external memory, minimizing network load by optimizing data transmission and integrity verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct memory access (DMA) mechanism is used between acceleration device and external memory, then data interchange capability is improved, but network load increases sharply
Solution Approach 1:
The patent introduces a DMA bridge as an intermediary device between the acceleration device and external memory. This bridge handles memory access requests locally without requiring network communication, thereby maintaining high data interchange capability while preventing network load increase. The DMA bridge acts as a mediator that intercepts and processes memory access requests before they can overwhelm the network infrastructure.
2Productivity
If hardware acceleration device processes large amount of data, then processing performance is improved, but memory capacity requirement increases
Solution Approach 1:
The patent segments the memory system into multiple components: on-chip memory within the acceleration device for frequently accessed data, external memory for bulk data storage, and a DMA bridge for coordinated access. This segmentation allows the system to process large amounts of data by distributing data across different memory hierarchies, maintaining high processing performance while managing overall memory capacity requirements efficiently.
3Device complexity
If network node is minimized, then system complexity is reduced, but data transmission capability may be limited
Solution Approach 1:
The DMA bridge serves as a local intermediary that enables high-capacity data transmission between the acceleration device and external memory without requiring network infrastructure. This eliminates the need for network nodes in the data path, reducing system complexity while maintaining robust data transmission capability through dedicated point-to-point communication channels.
Data Source
AI summary
Provided are a serial communication device and a serial communication system for a memory access. The serial communication device for a memory access may include: a system-on-chip (SoC) bus interface receiving a request transaction from a hardware acceleration device; a master protocol processor converting a request transaction received through the SoC bus interface into a packet according to a predetermined packet protocol; and a serial transceiver serial-transmitting the packet.