Serial Communications Unit Delay Control

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Solution Overview

Problem

In serial communications systems connected in a daisy chain fashion, variations in delay times due to asynchronous clock switching between slave devices reduce synchronization precision, especially when handling high-frequency serial data, making it difficult to maintain synchronization between master and slave devices.

Innovation Solution

A serial communications unit that includes a first conversion unit to convert reception serial data into synchronized parallel data, a memory unit to store this data, a reception delay time calculating unit to determine the reception start timing, and a timing control output unit to ensure a constant delay time from reception to transmission by synchronizing with a reference parallel clock pulse signal, thereby controlling the transmission start timing to maintain synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If serial data is converted into parallel data and handled with a parallel clock pulse signal obtained by dividing the communications frequency, then handling of serial data at high frequency becomes easier, but the variation in delay times becomes greater

Engineering Contradiction:
Improvehandling of serial dataVSAvoidsynchronization precision
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by calculating the delay time variation in advance through a delay time variation calculating unit, and then using this pre-calculated value to adjust the transmission timing. This allows the system to compensate for the increased delay variation caused by parallel conversion before transmission occurs, thereby maintaining synchronization precision while enabling easier handling of high-frequency serial data through parallel conversion

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the communications frequency becomes high, then the variation in delay times due to switching decreases, but handling of serial data becomes difficult

Engineering Contradiction:
Improvedelay time variationVSAvoidhandling of serial data
Core Design Contradiction:
Manufacturing precisionVSEase of operation

Solution Approach 1:

The patent applies parameter changes by converting the communications frequency parameter into a divided parallel clock pulse signal parameter, enabling easier data handling. Simultaneously, it introduces a delay time variation calculation parameter that compensates for the increased delay variation, thus resolving the contradiction between ease of operation and delay time variation

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If serial data is temporarily converted into parallel data, then the serial data can be handled more easily, but the delay time variation depends on the frequency of the parallel clock pulse signal

Engineering Contradiction:
Improvehandling of serial dataVSAvoiddelay time variation
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent implements feedback by using a delay time variation calculating unit that continuously calculates the delay time variation based on the actual parallel clock pulse signal frequency, and feeds this information back to a transmission timing adjusting unit. This closed-loop feedback mechanism allows the system to dynamically compensate for delay variations while maintaining the benefits of parallel data handling

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10291443B2Serial communications unit and communication method for serial communications unit
Publication Date: 2019.05.14 FANUC LTD
  • US10291443B2 patent drawing
  • US10291443B2 patent drawing
  • US10291443B2 patent drawing

AI summary

A communication method for a serial communications unit converts reception serial data into reception parallel data, stores the reception parallel data in a memory unit, and calculates a reception delay time of a reception start timing at which reception of packets is started. In addition, the reception parallel data which is stored in the memory unit is read out, and transmission parallel data, in which a transmission delay time of a transmission start timing at which transmission of packets is started is controlled so that a delay time from the reception start timing of packets and until transmission of packets is started is made constant, is output in synchronism with a transmission parallel clock pulse signal, and the output transmission parallel data is converted into transmission serial data and then is transmitted.