Parallel-to-Serial Converter Using 90° Clock Phases to Cut Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional parallel-to-serial converters face challenges in high-frequency operations due to the use of low-frequency clock signals with different phases, which result in narrowed pulse widths, restricted data swing, and jitter issues caused by junction capacitances of pass gates.
Innovation Solution
A parallel-to-serial converter design that utilizes clock signals with a 90-degree phase difference to select and output data without processing them into pulse forms with narrower widths, eliminating the need for pass gates and thereby reducing jitter effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-frequency clock signals with different phases are used for data selection, then data can be selected in high-frequency operations, but the pulse widths are narrowed and data swing is restricted
Solution Approach 1:
The patent uses dynamic clock signal generation where selection clock signals are generated on-the-fly from parallel clock signals with different phases through logical operations (NAND gates and inverters). This dynamic generation allows the selection process to adapt to high-frequency operations while maintaining adequate pulse widths by controlling the logical combination timing rather than relying on fixed low-frequency clock signals.
Solution Approach 2:
The patent changes the parameters of clock signals by generating multiple clock signals with different phases (0°, 90°, 180°, 270°) and combining them through logical operations. This parameter transformation allows the system to achieve high-frequency data selection while maintaining proper pulse widths through the temporal distribution of high-level periods across different phase-shifted clock signals.
2Reliability
If clock signals are processed into pulse forms with narrower widths, then data can be selected without overlap, but data swing is restricted and jitter increases
Solution Approach 1:
The patent extracts the selection function from narrow pulse-width clock signals and distributes it across multiple clock signals with broader high-level periods but different phases. By using logical operations to combine these phase-shifted clock signals, the system achieves non-overlapping data selection without requiring narrow pulse widths, thereby eliminating the jitter caused by narrow pulse processing while maintaining selection accuracy.
3Adaptability or versatility
If pass gates are used for data selection, then data can be multiplexed, but junction capacitances cause jitter and restrict data swing
Solution Approach 1:
The patent substitutes the mechanical/passive data selection mechanism (pass gates with junction capacitances) with an active logical selection mechanism using NAND gates and inverters. This substitution replaces the physical switching action of pass gates with logical operations on phase-shifted clock signals, eliminating the jitter caused by junction capacitances while maintaining the data multiplexing capability through controlled logical AND operations.
Data Source
AI summary
A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.