Serial Converter Synchronization for In-Phase Sampling Clocks
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Solution Overview
Problem
Synchronizing fast analog-to-digital and/or digital-to-analog data converters operating at high frequencies, such as those in antenna arrays or I/Q modulation data communication systems, is challenging due to the complexity of ensuring all converters start in phase, especially at frequencies above 100 megahertz, leading to system complexity and performance degradation.
Innovation Solution
A method where converters form a serial chain, with a synchronization signal transmitted from one converter to another, and each converter adjusts its configuration to account for propagation delays, allowing precise synchronization of sampling clocks by selecting the correct active edge of the reference clock, reducing design complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a synchronization signal is distributed across all converters with precise propagation delay evaluation, then synchronization precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
Each converter autonomously determines its own synchronization configuration by detecting the synchronization signal and measuring its propagation delay independently. The converter self-configures its frequency divider initialization edge based on its measured delay, eliminating the need for external centralized configuration and reducing system complexity.
Solution Approach 2:
The invention changes the approach from fixed predetermined synchronization configuration to dynamic parameter adaptation. Each converter adjusts its synchronization parameters (specifically the initialization edge selection of the frequency divider) based on its measured propagation delay, allowing the system to adapt to varying physical configurations without increasing complexity.
2Measurement precision
If precise propagation delay evaluation is performed for each converter, then synchronization precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
Each converter independently measures its own propagation delay and automatically configures its synchronization parameters without requiring external calibration or manual adjustment. This self-configuring capability simplifies the manufacturing process, as each unit can be produced independently and will automatically adapt to its specific installation environment.
Solution Approach 2:
The converter performs preliminary measurement of the propagation delay during the initialization phase and configures its synchronization parameters before normal operation begins. This preliminary self-configuration eliminates the need for post-manufacturing calibration or complex assembly procedures.
3Reliability
If PLLs are used for synchronization, then synchronization is achieved, but jitter is introduced and temperature stability deteriorates
Solution Approach 1:
The invention extracts and eliminates the PLL component from the synchronization system. Instead of using PLLs to generate and synchronize sampling clocks, the system directly distributes a synchronization signal and has each converter independently configure its frequency divider based on measured propagation delay, removing the source of jitter and temperature instability.
Solution Approach 2:
The invention replaces the complex feedback-based PLL control mechanism with a simpler open-loop approach where converters independently measure delay and configure their frequency dividers. This substitution eliminates the dynamic feedback loops that introduce jitter and temperature sensitivity while maintaining synchronization reliability.
Data Source
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AI summary
In a data processing architecture comprising a control unit and converters CNj to be synchronised on an active edge of a common reference clock CLK, a synchronisation method involves the arrangement of the converters into at least one series chain, and a process of synchronising the converters by propagating a synchronisation signal SYNC-m emitted by the control unit, said signal being retransmitted as an output OUT by each converter after resynchronisation on a clock active edge, to a synchronisation input IN of a subsequent converter in the chain. Each converter comprises a configuration register REG of the synchronisation, comprising at least one polarity parameter Sel-edgej that sets the polarity of the reference clock edge for reliable detection of a synchronisation signal received at the input of the converter. A phase parameter Sel-shiftj also makes it possible to phase-synchronise the sampling clocks of n conversion cores of the converters working at a sampling frequency obtained by dividing the reference clock CLK frequency by n.