Serial CRC Communication for Address and Data Error Detection
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Solution Overview
Problem
Existing communication protocols increase the number of CRC values sent, leading to reduced communication efficiency due to individual calculations for target addresses, register addresses, and data during both data writing and reading, which also fail to effectively detect address errors.
Innovation Solution
A communication protocol that calculates a single CRC value for the combined signal sequence of target address, register address, and data during both writing and reading, using an arithmetic circuit to synchronize and verify the sequence for errors, reducing the number of CRC values sent and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual CRC values are calculated for target address, register address, and data during data writing and reading, then data error detection capability is improved, but communication efficiency deteriorates due to increased number of CRC values sent
Solution Approach 1:
The patent merges multiple separate CRC calculations (for target address, register address, and data) into a single CRC calculation for the entire signal sequence. This combining approach maintains comprehensive error detection capability while reducing the number of CRC values transmitted, thereby improving communication efficiency.
Solution Approach 2:
The patent implements a universal CRC calculation mechanism that handles multiple types of data (target address, register address, and data) through a single standardized process. This multi-functional approach eliminates the need for separate CRC calculations for each data type, reducing overhead while maintaining detection capability across all signal elements.
2Measurement precision
If multiple CRC values are transmitted for different signal elements, then detection precision is improved, but loss of time increases due to additional transmission overhead
Solution Approach 1:
The patent combines multiple CRC verification operations into a single CRC calculation performed on the entire signal sequence including target address, register address, and data. This merging reduces the number of separate CRC values that need to be transmitted and processed, thereby reducing transmission time while maintaining comprehensive error detection precision.
3Reliability
If separate CRC calculations are performed for each signal element, then reliability is improved, but device complexity increases due to multiple arithmetic circuits required
Solution Approach 1:
The patent merges the functionality of multiple separate arithmetic circuits (one for each signal element) into a single arithmetic circuit that processes the entire signal sequence. This consolidation maintains comprehensive error detection reliability while significantly reducing device complexity by eliminating redundant circuitry.
Solution Approach 2:
The patent designs a universal arithmetic circuit capable of handling multiple types of signal elements (target address, register address, data) through a single standardized calculation process. This multi-functional circuit replaces multiple specialized circuits, reducing overall device complexity while maintaining detection reliability.
Data Source
AI summary
A controller is configured to perform a serial communication with a target, and comprises an arithmetic circuit configured to calculate a CRC value of a signal sequence including an address of the target, an address of a storage circuit of the target, and a write data when the controller performs data writing to the storage circuit, and a communication circuit configured to transmit the address of the target, the address of the storage circuit, the write data, and the CRC value to the target. The arithmetic circuit is configured to hold a calculation value during a calculation when a positive acknowledgment is returned from the target.