Serial CRC Module for Variable Data and Polynomial Widths
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Solution Overview
Problem
Current communication modules face inefficiencies in calculating cyclic redundancy check (CRC) values for varying data sizes and polynomial sizes, leading to increased logic gates, size, cost, and power consumption, as well as latency issues.
Innovation Solution
A serial communication circuit with a CRC generation circuit that includes two CRC blocks, enabling CRC calculation for X-bit data units using X-bit and 2X-bit polynomials within specific clock cycles, reducing the need for additional logic gates and clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a same communication module calculates CRC values for different sizes of data units and different sized polynomials, then adaptability is improved, but device complexity increases due to increased numbers of logic gates
Solution Approach 1:
The patent implements dynamic CRC calculation by using a single configurable CRC circuit that can adapt its polynomial width (X-bit or 2X-bit) and data unit size (X-bit or 2X-bit) based on control signals. The circuit dynamically selects between different polynomial widths and data sizes without requiring separate dedicated circuits for each configuration, thereby maintaining adaptability while reducing overall device complexity.
Solution Approach 2:
The patent creates a universal CRC calculation circuit capable of performing multiple functions: calculating CRC for X-bit data units with X-bit polynomials, X-bit data units with 2X-bit polynomials, 2X-bit data units with X-bit polynomials, and 2X-bit data units with 2X-bit polynomials. This single multi-functional circuit replaces what would traditionally require four separate dedicated circuits, significantly reducing device complexity while maintaining full adaptability.
2Adaptability or versatility
If a same communication module calculates CRC values for different sizes of data units and different sized polynomials, then adaptability is improved, but use of energy increases due to increased numbers of logic gates
Solution Approach 1:
The patent implements dynamic CRC calculation by using a single configurable CRC circuit that can adapt its polynomial width (X-bit or 2X-bit) and data unit size (X-bit or 2X-bit) based on control signals. The circuit dynamically selects between different polynomial widths and data sizes without requiring separate dedicated circuits for each configuration, thereby maintaining adaptability while reducing overall device complexity.
Solution Approach 2:
The patent creates a universal CRC calculation circuit capable of performing multiple functions: calculating CRC for X-bit data units with X-bit polynomials, X-bit data units with 2X-bit polynomials, 2X-bit data units with X-bit polynomials, and 2X-bit data units with 2X-bit polynomials. This single multi-functional circuit replaces what would traditionally require four separate dedicated circuits, significantly reducing device complexity while maintaining full adaptability.
3Adaptability or versatility
If traditional CRC implementations accommodate different data sizes and polynomial sizes, then adaptability is improved, but latency increases due to increased numbers of clock cycles
Solution Approach 1:
The patent implements dynamic CRC calculation by using a single configurable CRC circuit that can adapt its polynomial width (X-bit or 2X-bit) and data unit size (X-bit or 2X-bit) based on control signals. The circuit dynamically selects between different polynomial widths and data sizes without requiring separate dedicated circuits for each configuration, thereby maintaining adaptability while reducing overall device complexity.
Solution Approach 2:
The patent employs preliminary action by pre-configuring the CRC circuit with both X-bit and 2X-bit polynomial capabilities and data unit handling capacity. Control logic is pre-established to automatically select the appropriate polynomial width and data size configuration before calculation begins, eliminating the need for sequential reconfiguration or multiple calculation passes, thereby reducing latency.
4Adaptability or versatility
If traditional CRC implementations accommodate different data sizes and polynomial sizes, then adaptability is improved, but device complexity increases leading to increased cost
Solution Approach 1:
The patent implements dynamic CRC calculation by using a single configurable CRC circuit that can adapt its polynomial width (X-bit or 2X-bit) and data unit size (X-bit or 2X-bit) based on control signals. The circuit dynamically selects between different polynomial widths and data sizes without requiring separate dedicated circuits for each configuration, thereby maintaining adaptability while reducing overall device complexity.
Solution Approach 2:
The patent creates a universal CRC calculation circuit capable of performing multiple functions: calculating CRC for X-bit data units with X-bit polynomials, X-bit data units with 2X-bit polynomials, 2X-bit data units with X-bit polynomials, and 2X-bit data units with 2X-bit polynomials. This single multi-functional circuit replaces what would traditionally require four separate dedicated circuits, significantly reducing device complexity while maintaining full adaptability.
Data Source
AI summary
A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.


