Switched-Capacitor Serial DAC With Higher-Order Interpolation
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Solution Overview
Problem
Existing digital to analog converters (DACs) face challenges in filtering signal images at harmonics of the sampling frequency, particularly for wide-band signals, as they require high oversampling ratios that increase system complexity and power consumption, and current solutions like zero-order hold and cubic Lagrangian interpolation are inefficient.
Innovation Solution
A variable step serial DAC using switched capacitor CMOS circuits achieves higher order interpolation without a sample and hold circuit, employing dynamically programmable capacitor arrays to define the output voltage trajectory through incremental charge transfer, minimizing energy and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If oversampling is used to filter signal images, then filtering performance is improved, but system complexity and power consumption increase
Solution Approach 1:
The patent changes the fundamental parameter of interpolation order from zero-order (conventional) to higher-order (second-order or above) by modifying the capacitor charge transfer equations. This allows achieving superior filtering performance without increasing oversampling ratio, thereby reducing system complexity while maintaining image rejection capability
Solution Approach 2:
The patent introduces dynamically programmable capacitor arrays that can be reconfigured to implement different interpolation orders and trajectories. This dynamic capability allows the system to adapt the filtering characteristics without hardware changes, achieving high-performance filtering with flexible complexity management
2Measurement precision
If higher oversampling ratios are used for wide-band signals, then filtering performance is improved, but power consumption increases
Solution Approach 1:
By changing the interpolation order parameter from zero-order to higher-order in the charge transfer equations, the patent achieves superior filtering for wide-band signals without increasing the oversampling ratio. This parameter change eliminates the need for high-oversampling operations that would otherwise be required, thereby reducing power consumption while maintaining filtering performance
Solution Approach 2:
The patent replaces the conventional mechanical approach of increasing oversampling ratio (which requires faster switching and higher power) with a mathematical approach of higher-order interpolation. This substitution achieves the same filtering goal through algorithmic complexity rather than operational speed, significantly reducing power consumption
3Measurement precision
If cubic Lagrangian interpolation with CIC filters is used, then filtering performance is improved, but power and area consumption increase
Solution Approach 1:
The patent extracts and eliminates the power-consuming adder and multiplier operations from the interpolation process by implementing higher-order interpolation through pure capacitor charge transfer in the analog domain. This extraction of computational operations removes the primary sources of power consumption while maintaining filtering performance
Solution Approach 2:
The patent substitutes the digital computational system (adders and multipliers) with an analog capacitor-based charge transfer system. This substitution eliminates the need for power-hungry digital computation while achieving the same or superior interpolation function through physical charge redistribution
4Measurement precision
If digital interpolation with adders and multipliers is used, then interpolation accuracy is improved, but area consumption increases
Solution Approach 1:
The patent substitutes the area-consuming digital computational hardware (adders and multipliers) with compact analog capacitor arrays. The higher-order interpolation is achieved through the spatial arrangement and charge transfer between capacitors rather than through computational operations, dramatically reducing the required silicon area while maintaining or improving interpolation accuracy
Solution Approach 2:
The patent extracts and removes the area-consuming digital computation units from the interpolation architecture. By taking out the adders and multipliers and replacing them with pure capacitor-based charge transfer, the patent achieves high-precision interpolation with minimal area occupation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides superior output performance by achieving desired filtering with reduced power and area consumption, enabling efficient handling of wide-band signals without the need for high oversampling ratios.
Implementation Method 1
Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval
Data Source
AI summary
A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.